From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50384) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XIGE4-0004cW-DP for qemu-devel@nongnu.org; Fri, 15 Aug 2014 08:03:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XIGDz-0000hV-3s for qemu-devel@nongnu.org; Fri, 15 Aug 2014 08:03:20 -0400 Received: from mail-la0-f48.google.com ([209.85.215.48]:60320) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XIGDy-0000hA-TP for qemu-devel@nongnu.org; Fri, 15 Aug 2014 08:03:15 -0400 Received: by mail-la0-f48.google.com with SMTP id gl10so2197151lab.21 for ; Fri, 15 Aug 2014 05:03:13 -0700 (PDT) Date: Fri, 15 Aug 2014 14:03:22 +0200 From: Christoffer Dall Message-ID: <20140815120322.GW10550@cbox> References: <1407056027-7522-1-git-send-email-adam@os.inf.tu-dresden.de> <1407056027-7522-2-git-send-email-adam@os.inf.tu-dresden.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1407056027-7522-2-git-send-email-adam@os.inf.tu-dresden.de> Subject: Re: [Qemu-devel] [PATCH 1/3] arm_gic: Fix read of GICD_ICFGR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Adam Lackorzynski Cc: qemu-devel@nongnu.org On Sun, Aug 03, 2014 at 10:53:45AM +0200, Adam Lackorzynski wrote: > The GICD_ICFGR register covers 4 interrupts per byte. > > Signed-off-by: Adam Lackorzynski > --- > hw/intc/arm_gic.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 1532ef9..d2b1aaf 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -372,7 +372,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) > } > } else if (offset < 0xf00) { > /* Interrupt Configuration. */ > - irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ; > + irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ; > if (irq >= s->num_irq) > goto bad_reg; > res = 0; > -- > 2.0.1 > > I guess we should consider only getting/setting the LSB of each field if we're emulating a GICv1, but: Acked-by: Christoffer Dall