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Date: Fri, 15 Aug 2014 14:07:14 +0200
From: Christoffer Dall <christoffer.dall@linaro.org>
Message-ID: <20140815120714.GA19635@cbox>
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Subject: Re: [Qemu-devel] [PATCH 2/3] arm_gic: SGIs for GICD_ICFGR are WI
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To: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
Cc: qemu-devel@nongnu.org

On Sun, Aug 03, 2014 at 10:53:46AM +0200, Adam Lackorzynski wrote:
> Writes to SGIs for GICD_ICFGR register must be ignored.
> 
> Signed-off-by: Adam Lackorzynski <adam@os.inf.tu-dresden.de>
> ---
>  hw/intc/arm_gic.c | 11 +++++++----
>  1 file changed, 7 insertions(+), 4 deletions(-)
> 
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index d2b1aaf..cd6e6ea 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -566,10 +566,13 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
>              } else {
>                  GIC_CLEAR_MODEL(irq + i);
>              }
> -            if (value & (2 << (i * 2))) {
> -                GIC_SET_EDGE_TRIGGER(irq + i);
> -            } else {
> -                GIC_CLEAR_EDGE_TRIGGER(irq + i);
> +            /* SGIs are WI */

They're actually WI/RAO, so we should set them to edge-triggered
somewhere or always return 1 for reads of these values as well as part
of this fix.

> +            if (irq >= 16) {
> +                if (value & (2 << (i * 2))) {
> +                    GIC_SET_EDGE_TRIGGER(irq + i);
> +                } else {
> +                    GIC_CLEAR_EDGE_TRIGGER(irq + i);
> +                }
>              }
>          }
>      } else if (offset < 0xf10) {
> -- 
> 2.0.1
> 
>