From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39427) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XIjzc-0001X2-KL for qemu-devel@nongnu.org; Sat, 16 Aug 2014 15:50:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XIjzW-0007df-Vo for qemu-devel@nongnu.org; Sat, 16 Aug 2014 15:50:24 -0400 Received: from os.inf.tu-dresden.de ([2002:8d4c:3001:48::99]:37764) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XIjzW-0007da-MX for qemu-devel@nongnu.org; Sat, 16 Aug 2014 15:50:18 -0400 Date: Sat, 16 Aug 2014 21:50:16 +0200 From: Adam Lackorzynski Message-ID: <20140816195016.GC27311@os.inf.tu-dresden.de> References: <1407056027-7522-1-git-send-email-adam@os.inf.tu-dresden.de> <1407056027-7522-3-git-send-email-adam@os.inf.tu-dresden.de> <20140815121217.GB19635@cbox> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline In-Reply-To: <20140815121217.GB19635@cbox> Subject: Re: [Qemu-devel] [PATCH 2/3] arm_gic: SGIs for GICD_ICFGR are WI List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Christoffer Dall Cc: qemu-devel@nongnu.org On Fri Aug 15, 2014 at 14:12:17 +0200, Christoffer Dall wrote: > On Sun, Aug 03, 2014 at 10:53:46AM +0200, Adam Lackorzynski wrote: > > Writes to SGIs for GICD_ICFGR register must be ignored. > > > > Signed-off-by: Adam Lackorzynski > > --- > > hw/intc/arm_gic.c | 11 +++++++---- > > 1 file changed, 7 insertions(+), 4 deletions(-) > > > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > > index d2b1aaf..cd6e6ea 100644 > > --- a/hw/intc/arm_gic.c > > +++ b/hw/intc/arm_gic.c > > @@ -566,10 +566,13 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, > > } else { > > GIC_CLEAR_MODEL(irq + i); > > } > > - if (value & (2 << (i * 2))) { > > - GIC_SET_EDGE_TRIGGER(irq + i); > > - } else { > > - GIC_CLEAR_EDGE_TRIGGER(irq + i); > > + /* SGIs are WI */ > > + if (irq >= 16) { > > + if (value & (2 << (i * 2))) { > > + GIC_SET_EDGE_TRIGGER(irq + i); > > + } else { > > + GIC_CLEAR_EDGE_TRIGGER(irq + i); > > + } > > } > > } > > } else if (offset < 0xf10) { > > Actually, this looks a bit weird given that you do set the model bit, > which should probably be treated as WI/RAZ for a GICv2 emulation, but > you don't set the edge trigger bit for them. I've addressed that in a separate patch now. However, I'm not sure got the revision check right. Comments appreciated! > I think a cleaner fix might be to to just change the existing check from > (irq < GIC_INTERNAL) to (irq < GIT_NR_SGIS), then you also don't need > the next patch. Ok, new series sent out. Adam -- Adam adam@os.inf.tu-dresden.de Lackorzynski http://os.inf.tu-dresden.de/~adam/