From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32907) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJCZx-0006yo-FF for qemu-devel@nongnu.org; Sun, 17 Aug 2014 22:21:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XJCZr-0008Jj-C6 for qemu-devel@nongnu.org; Sun, 17 Aug 2014 22:21:49 -0400 Received: from mail-pd0-x229.google.com ([2607:f8b0:400e:c02::229]:44381) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XJCZr-0008Jd-4I for qemu-devel@nongnu.org; Sun, 17 Aug 2014 22:21:43 -0400 Received: by mail-pd0-f169.google.com with SMTP id y10so6569279pdj.0 for ; Sun, 17 Aug 2014 19:21:41 -0700 (PDT) Date: Mon, 18 Aug 2014 12:18:43 +1000 From: "Edgar E. Iglesias" Message-ID: <20140818021843.GF13728@toto> References: <2b30c3cba10c4cb7fe7e769fe9a7db8849ae3c63.1408326727.git.peter.crosthwaite@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2b30c3cba10c4cb7fe7e769fe9a7db8849ae3c63.1408326727.git.peter.crosthwaite@xilinx.com> Subject: Re: [Qemu-devel] [PATCH target-arm v1 1/1] arm: cortex-a9: Fix cache-line size List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org On Sun, Aug 17, 2014 at 06:59:59PM -0700, Peter Crosthwaite wrote: > Caches are 16 bytes in A9. Self identify in CCSIDR accordingly. Hi, This is a bit confusing, caches are not 16bytes on the a9, they are configurable. Cache lines are 32 bytes. The reported associativity doesn't match either. For 16KB caches (as the comment in the code indicates), I think you want the lower bits to be fe01c. Cheers, Edgar > > QEMU doesn't emulate caches, but we should still report the correct > cache-line size to the guest. Some guests (like u-boot) complain if > the cache-line size mismatches a requested flush or invalidate > operation. > > Signed-off-by: Peter Crosthwaite > --- > > target-arm/cpu.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target-arm/cpu.c b/target-arm/cpu.c > index 7cebb76..f49130a 100644 > --- a/target-arm/cpu.c > +++ b/target-arm/cpu.c > @@ -713,8 +713,8 @@ static void cortex_a9_initfn(Object *obj) > cpu->id_isar3 = 0x11112131; > cpu->id_isar4 = 0x00111142; > cpu->clidr = (1 << 27) | (1 << 24) | 3; > - cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */ > - cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */ > + cpu->ccsidr[0] = 0xe00fe011; /* 16k L1 dcache. */ > + cpu->ccsidr[1] = 0x200fe011; /* 16k L1 icache. */ > define_arm_cp_regs(cpu, cortexa9_cp_reginfo); > } > > -- > 2.0.1.1.gfbfc394 > >