[Qemu-devel] [PATCH target-arm v1 1/1] arm: cortex-a9: Fix cache-line size

[Qemu-devel] [PATCH target-arm v1 1/1] arm: cortex-a9: Fix cache-line size

[Peter Crosthwaite]

Caches are 16 bytes in A9. Self identify in CCSIDR accordingly.

QEMU doesn't emulate caches, but we should still report the correct
cache-line size to the guest. Some guests (like u-boot) complain if
the cache-line size mismatches a requested flush or invalidate
operation.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
---

 target-arm/cpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 7cebb76..f49130a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -713,8 +713,8 @@ static void cortex_a9_initfn(Object *obj)
     cpu->id_isar3 = 0x11112131;
     cpu->id_isar4 = 0x00111142;
     cpu->clidr = (1 << 27) | (1 << 24) | 3;
-    cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
-    cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
+    cpu->ccsidr[0] = 0xe00fe011; /* 16k L1 dcache. */
+    cpu->ccsidr[1] = 0x200fe011; /* 16k L1 icache. */
     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 }
 
-- 
2.0.1.1.gfbfc394

Re: [Qemu-devel] [PATCH target-arm v1 1/1] arm: cortex-a9: Fix cache-line size

[Edgar E. Iglesias]

On Sun, Aug 17, 2014 at 06:59:59PM -0700, Peter Crosthwaite wrote:
> Caches are 16 bytes in A9. Self identify in CCSIDR accordingly.

Hi,

This is a bit confusing, caches are not 16bytes on the a9, they are configurable.
Cache lines are 32 bytes. The reported associativity doesn't match
either. For 16KB caches (as the comment in the code indicates),
I think you want the lower bits to be fe01c.

Cheers,
Edgar


> 
> QEMU doesn't emulate caches, but we should still report the correct
> cache-line size to the guest. Some guests (like u-boot) complain if
> the cache-line size mismatches a requested flush or invalidate
> operation.
> 
> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
> ---
> 
>  target-arm/cpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 7cebb76..f49130a 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -713,8 +713,8 @@ static void cortex_a9_initfn(Object *obj)
>      cpu->id_isar3 = 0x11112131;
>      cpu->id_isar4 = 0x00111142;
>      cpu->clidr = (1 << 27) | (1 << 24) | 3;
> -    cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
> -    cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
> +    cpu->ccsidr[0] = 0xe00fe011; /* 16k L1 dcache. */
> +    cpu->ccsidr[1] = 0x200fe011; /* 16k L1 icache. */
>      define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
>  }
>  
> -- 
> 2.0.1.1.gfbfc394
> 
> 

Re: [Qemu-devel] [PATCH target-arm v1 1/1] arm: cortex-a9: Fix cache-line size

[Peter Crosthwaite]

On Mon, Aug 18, 2014 at 12:18 PM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> On Sun, Aug 17, 2014 at 06:59:59PM -0700, Peter Crosthwaite wrote:
>> Caches are 16 bytes in A9. Self identify in CCSIDR accordingly.
>
> Hi,
>
> This is a bit confusing, caches are not 16bytes on the a9, they are configurable.

Sorry my bad. Should read "cache-line" and "32-bytes". Will fix in v2.
I agree about about the configurability of the actual cache size but
not touching that this patch.

> Cache lines are 32 bytes. The reported associativity doesn't match
> either.

For 16KB caches (as the comment in the code indicates),
> I think you want the lower bits to be fe01c.

Splitting that out, associativity = 3 (+1 = 4 for a9 4x assoc caching)
which is correct. Will update that next spin. But line size field = 4
which would correspond to line size of 256B.

I think line size needs to be 1 as in this patch but the other fields
need tweaking.

Adding in your assoc fix though we should now have 0x19. in lower
fields. Then num-sets =

16k / 4 assoc / 32 line sz = 128 so add in 0xfe000.

I think the magic number is 0xfe019.

Regards,
Peter

>
> Cheers,
> Edgar
>
>
>>
>> QEMU doesn't emulate caches, but we should still report the correct
>> cache-line size to the guest. Some guests (like u-boot) complain if
>> the cache-line size mismatches a requested flush or invalidate
>> operation.
>>
>> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
>> ---
>>
>>  target-arm/cpu.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
>> index 7cebb76..f49130a 100644
>> --- a/target-arm/cpu.c
>> +++ b/target-arm/cpu.c
>> @@ -713,8 +713,8 @@ static void cortex_a9_initfn(Object *obj)
>>      cpu->id_isar3 = 0x11112131;
>>      cpu->id_isar4 = 0x00111142;
>>      cpu->clidr = (1 << 27) | (1 << 24) | 3;
>> -    cpu->ccsidr[0] = 0xe00fe015; /* 16k L1 dcache. */
>> -    cpu->ccsidr[1] = 0x200fe015; /* 16k L1 icache. */
>> +    cpu->ccsidr[0] = 0xe00fe011; /* 16k L1 dcache. */
>> +    cpu->ccsidr[1] = 0x200fe011; /* 16k L1 icache. */
>>      define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
>>  }
>>
>> --
>> 2.0.1.1.gfbfc394
>>
>>
>

Re: [Qemu-devel] [PATCH target-arm v1 1/1] arm: cortex-a9: Fix cache-line size

[Edgar E. Iglesias]

On Mon, Aug 18, 2014 at 12:57:43PM +1000, Peter Crosthwaite wrote:
> On Mon, Aug 18, 2014 at 12:18 PM, Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> > On Sun, Aug 17, 2014 at 06:59:59PM -0700, Peter Crosthwaite wrote:
> >> Caches are 16 bytes in A9. Self identify in CCSIDR accordingly.
> >
> > Hi,
> >
> > This is a bit confusing, caches are not 16bytes on the a9, they are configurable.
> 
> Sorry my bad. Should read "cache-line" and "32-bytes". Will fix in v2.
> I agree about about the configurability of the actual cache size but
> not touching that this patch.
> 
> > Cache lines are 32 bytes. The reported associativity doesn't match
> > either.
> 
> For 16KB caches (as the comment in the code indicates),
> > I think you want the lower bits to be fe01c.
> 
> Splitting that out, associativity = 3 (+1 = 4 for a9 4x assoc caching)
> which is correct. Will update that next spin. But line size field = 4
> which would correspond to line size of 256B.
> 
> I think line size needs to be 1 as in this patch but the other fields
> need tweaking.
> 
> Adding in your assoc fix though we should now have 0x19. in lower
> fields. Then num-sets =
> 
> 16k / 4 assoc / 32 line sz = 128 so add in 0xfe000.
> 
> I think the magic number is 0xfe019.

Yes, agreed.

Cheers,
Edgar