From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:52448)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <edgar.iglesias@gmail.com>) id 1XJiPo-0006Og-TS
	for qemu-devel@nongnu.org; Tue, 19 Aug 2014 08:21:33 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <edgar.iglesias@gmail.com>) id 1XJiPk-0004hB-3I
	for qemu-devel@nongnu.org; Tue, 19 Aug 2014 08:21:28 -0400
Received: from mail-pa0-x22b.google.com ([2607:f8b0:400e:c03::22b]:60695)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <edgar.iglesias@gmail.com>) id 1XJiPj-0004gy-Sb
	for qemu-devel@nongnu.org; Tue, 19 Aug 2014 08:21:24 -0400
Received: by mail-pa0-f43.google.com with SMTP id lf10so9724853pab.2
	for <qemu-devel@nongnu.org>; Tue, 19 Aug 2014 05:21:18 -0700 (PDT)
Date: Tue, 19 Aug 2014 22:20:05 +1000
From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Message-ID: <20140819122005.GC27221@zapo.iiNet>
References: <1407500294-10804-1-git-send-email-peter.maydell@linaro.org>
	<1407500294-10804-10-git-send-email-peter.maydell@linaro.org>
	<20140819095617.GG13728@toto>
	<CAFEAcA-ckVUT7N8HB6ZXoBN0eojdmo3ZhzsKhZR4WVEYNmyR3w@mail.gmail.com>
	<CAFEAcA-aP2DWyzg0qXaWysuGVPyHz4zaeefS9j73CBPC4eJnYw@mail.gmail.com>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <CAFEAcA-aP2DWyzg0qXaWysuGVPyHz4zaeefS9j73CBPC4eJnYw@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 09/11] target-arm: Implement ARMv8
 single-step handling for A64 code
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>, David Long <dave.long@linaro.org>

On Tue, Aug 19, 2014 at 11:46:23AM +0100, Peter Maydell wrote:
> On 19 August 2014 11:25, Peter Maydell <peter.maydell@linaro.org> wrote:
> > On 19 August 2014 10:56, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
> >> On Fri, Aug 08, 2014 at 01:18:12PM +0100, Peter Maydell wrote:
> >>> --- a/target-arm/cpu.h
> >>> +++ b/target-arm/cpu.h
> >>> @@ -1211,6 +1211,10 @@ static inline bool arm_singlestep_active(CPUARMState *env)
> >>>  #define ARM_TBFLAG_AA64_EL_MASK     (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
> >>>  #define ARM_TBFLAG_AA64_FPEN_SHIFT  2
> >>>  #define ARM_TBFLAG_AA64_FPEN_MASK   (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
> >>> +#define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
> >>> +#define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
> >>> +#define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 3
> >>> +#define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
> >>
> >> Shouldn't these shifts/masks differ?
> >
> > Oops. Yes, they certainly should.
> 
> The fix is just a simple s/3/4/ for the PSTATE_SS_SHIFT
> define. Does anybody want a retransmit of the series for
> this one-liner?

Hi,

AFAICT, the rest of the series looks good, RB on all.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

No need to repost for me.

Cheers,
Edgar