From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XMAya-0003FI-QV for qemu-devel@nongnu.org; Tue, 26 Aug 2014 03:15:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XMAyU-0005bS-KB for qemu-devel@nongnu.org; Tue, 26 Aug 2014 03:15:32 -0400 Received: from mail.ispras.ru ([83.149.199.45]:33291) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XMAyU-0005bN-CP for qemu-devel@nongnu.org; Tue, 26 Aug 2014 03:15:26 -0400 From: Pavel Dovgalyuk Date: Tue, 26 Aug 2014 11:15:25 +0400 Message-ID: <20140826071525.1672.14717.stgit@PASHA-ISP> In-Reply-To: <20140826071427.1672.48119.stgit@PASHA-ISP> References: <20140826071427.1672.48119.stgit@PASHA-ISP> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 10/12] piix: do not raise irq while loading vmstate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, zealot351@gmail.com, maria.klimushenkova@ispras.ru, pavel.dovgaluk@ispras.ru This patch disables raising an irq while loading the state of PCI bridge. Signed-off-by: Pavel Dovgalyuk --- hw/pci-host/piix.c | 22 ++++++++++++++++++++-- 1 files changed, 20 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index e0e0946..86d6d20 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -409,7 +409,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -422,6 +422,18 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); piix3->pic_levels &= ~mask; piix3->pic_levels |= mask * !!level; +} + +static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +{ + int pic_irq; + + pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; + if (pic_irq >= PIIX_NUM_PIC_IRQS) { + return; + } + + piix3_set_irq_level_internal(piix3, pirq, level); piix3_set_irq_pic(piix3, pic_irq); } @@ -527,7 +539,13 @@ static void piix3_reset(void *opaque) static int piix3_post_load(void *opaque, int version_id) { PIIX3State *piix3 = opaque; - piix3_update_irq_levels(piix3); + int pirq; + + piix3->pic_levels = 0; + for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { + piix3_set_irq_level_internal(piix3, pirq, + pci_bus_get_irq_level(piix3->dev.bus, pirq)); + } return 0; }