From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56146) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XMxjh-000154-6y for qemu-devel@nongnu.org; Thu, 28 Aug 2014 07:19:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XMxja-0007l4-GL for qemu-devel@nongnu.org; Thu, 28 Aug 2014 07:19:25 -0400 Received: from mail.ispras.ru ([83.149.199.45]:55534) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XMxja-0007kq-9Y for qemu-devel@nongnu.org; Thu, 28 Aug 2014 07:19:18 -0400 From: Pavel Dovgalyuk Date: Thu, 28 Aug 2014 15:19:19 +0400 Message-ID: <20140828111919.1624.72278.stgit@PASHA-ISP> In-Reply-To: <20140828111822.1624.24556.stgit@PASHA-ISP> References: <20140828111822.1624.24556.stgit@PASHA-ISP> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH v2 10/12] piix: do not raise irq while loading vmstate List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, zealot351@gmail.com, maria.klimushenkova@ispras.ru, pavel.dovgaluk@ispras.ru This patch disables raising an irq while loading the state of PCI bridge. The aim of this patch is preserving the same behavior while saving and restoring the VM state. IRQ is not raised while saving the state of the bridge. That's why the behavior of the restored system will differ from the original one. This patch eliminates raising an irq and just restores the calculated state fields in post_load function. Signed-off-by: Pavel Dovgalyuk --- hw/pci-host/piix.c | 26 ++++++++++++++++++++++++-- 1 files changed, 24 insertions(+), 2 deletions(-) diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index e0e0946..cd50435 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -409,7 +409,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) (pic_irq * PIIX_NUM_PIRQS)))); } -static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level) { int pic_irq; uint64_t mask; @@ -422,6 +422,18 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq); piix3->pic_levels &= ~mask; piix3->pic_levels |= mask * !!level; +} + +static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) +{ + int pic_irq; + + pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; + if (pic_irq >= PIIX_NUM_PIC_IRQS) { + return; + } + + piix3_set_irq_level_internal(piix3, pirq, level); piix3_set_irq_pic(piix3, pic_irq); } @@ -527,7 +539,17 @@ static void piix3_reset(void *opaque) static int piix3_post_load(void *opaque, int version_id) { PIIX3State *piix3 = opaque; - piix3_update_irq_levels(piix3); + int pirq; + + /* Update irq levels without raising an interrupt which + could be caused by piix3_update_irq_levels function. + Raising an irq will switch the system to the state + different to the saved one. */ + piix3->pic_levels = 0; + for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { + piix3_set_irq_level_internal(piix3, pirq, + pci_bus_get_irq_level(piix3->dev.bus, pirq)); + } return 0; }