From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37496) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXHLu-0001Ek-8v for qemu-devel@nongnu.org; Thu, 25 Sep 2014 18:17:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XXHLo-0004OJ-8s for qemu-devel@nongnu.org; Thu, 25 Sep 2014 18:17:30 -0400 Received: from mail-qg0-x22d.google.com ([2607:f8b0:400d:c04::22d]:47775) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XXHLo-0004M8-22 for qemu-devel@nongnu.org; Thu, 25 Sep 2014 18:17:24 -0400 Received: by mail-qg0-f45.google.com with SMTP id q108so8305645qgd.4 for ; Thu, 25 Sep 2014 15:17:17 -0700 (PDT) Date: Fri, 26 Sep 2014 08:12:36 +1000 From: "Edgar E. Iglesias" Message-ID: <20140925221236.GR16081@toto> References: <1410582564-27687-1-git-send-email-edgar.iglesias@gmail.com> <1410582564-27687-3-git-send-email-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v6 02/10] target-arm: Add SCR_EL3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Rob Herring , Peter Crosthwaite , Fabian Aggeler , QEMU Developers , Alexander Graf , Greg Bellows , Paolo Bonzini , Alex =?iso-8859-1?Q?Benn=E9e?= , Christoffer Dall , Richard Henderson On Thu, Sep 25, 2014 at 07:15:29PM +0100, Peter Maydell wrote: > On 13 September 2014 05:29, Edgar E. Iglesias wrote: > > From: "Edgar E. Iglesias" > > > > Signed-off-by: Edgar E. Iglesias > > --- > > target-arm/cpu.h | 19 ++++++++++++++++++- > > target-arm/helper.c | 35 +++++++++++++++++++++++++++++++++-- > > 2 files changed, 51 insertions(+), 3 deletions(-) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index 36507f9..c69d471 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -172,7 +172,6 @@ typedef struct CPUARMState { > > uint64_t c1_sys; /* System control register. */ > > uint64_t c1_coproc; /* Coprocessor access register. */ > > uint32_t c1_xscaleauxcr; /* XScale auxiliary control register. */ > > - uint32_t c1_scr; /* secure config register. */ > > uint64_t ttbr0_el1; /* MMU translation table base 0. */ > > uint64_t ttbr1_el1; /* MMU translation table base 1. */ > > uint64_t c2_control; /* MMU translation table base control. */ > > @@ -185,6 +184,7 @@ typedef struct CPUARMState { > > uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ > > uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ > > uint64_t hcr_el2; /* Hypervisor configuration register */ > > + uint64_t scr_el3; /* Secure configuration register. */ > > uint32_t ifsr_el2; /* Fault status registers. */ > > uint64_t esr_el[4]; > > uint32_t c6_region[8]; /* MPU base/size registers. */ > > > @@ -873,8 +899,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { > > .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]), > > .resetvalue = 0 }, > > { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, > > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), > > - .resetvalue = 0, }, > > + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), > > + .resetvalue = 0, .writefn = scr_write }, > > Still wrong, I'm afraid. For a 32 bit register with a 64 > bit struct field you have to use offsetoflow32(), otherwise > you'll get the wrong half on bigendian hosts. Fixed for v7, thanks.