From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44112) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XYdXP-0000dB-UZ for qemu-devel@nongnu.org; Mon, 29 Sep 2014 12:11:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XYdXL-0004Oz-4A for qemu-devel@nongnu.org; Mon, 29 Sep 2014 12:10:59 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44988) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XYdXK-0004OK-SR for qemu-devel@nongnu.org; Mon, 29 Sep 2014 12:10:55 -0400 Date: Mon, 29 Sep 2014 19:14:06 +0300 From: "Michael S. Tsirkin" Message-ID: <20140929161406.GB21268@redhat.com> References: <1409578159-9576-1-git-send-email-arei.gonglei@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1409578159-9576-1-git-send-email-arei.gonglei@huawei.com> Subject: Re: [Qemu-devel] [PATCH v3 0/3] add check for PCIe root ports and downstream ports List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: arei.gonglei@huawei.com Cc: peter.crosthwaite@xilinx.com, weidong.huang@huawei.com, marcel.a@redhat.com, armbru@redhat.com, luonengjun@huawei.com, qemu-devel@nongnu.org, peter.huangpeng@huawei.com, imammedo@redhat.com, pbonzini@redhat.com, afaerber@suse.de On Mon, Sep 01, 2014 at 09:29:16PM +0800, arei.gonglei@huawei.com wrote: > From: Gonglei > > Root ports and downstream ports of switches are the hot > pluggable ports in a PCI Express hierarchy. > PCI Express supports chip-to-chip interconnect, a PCIe link can > only connect one pci device/Switch/EndPoint or PCI-bridge. > > 7.3. Configuration Transaction Rules (PCI Express specification 3.0) > 7.3.1. Device Number > > Downstream Ports that do not have ARI Forwarding enabled must > associate only Device 0 with the device attached to the Logical Bus > representing the Link from the Port. > > In QEMU, ARI Forwarding is enabled defualt at emulation of PCIe > ports. ARI Forwarding enable setting at firmware/OS Control handoff. > If the bit is Set when a non-ARI Device is present, the non-ARI > Device can respond to Configuration Space accesses under what it > interprets as being different Device Numbers, and its Functions can > be aliased under multiple Device Numbers, generally leading to > undesired behavior. > > So, for pci devices attached in pcie root ports or downstream pots, > we shoud assure that its slot is non-zero. For pcie devcies, which > ARP capbility is not enabled, we also should assure that its slot > is non-zero. So what is this patchset about? Is there a broken configuration that this helps prevent? Can you show the command-line please? In particular, non-express devices behind an express bus shouldn't exist according to spec, but do in practice, and guests seem to be able to handle them. > Changes since v2: > - make patch 1/3 more simpler and safer.(Hu Tao) > - change check logic from pci.c to pcie.c and change function's name > - judge devcies' ARI capbility instead of PCIe ports' ARI Forwarding > (Michael) > - add trivial patch 3/3 > - update patch's commit messages and code comments. > > Thanks for your reviewing. > > Changes since v1: > - using object_dynamic_cast() instead of simple string comparing (Paolo) > - add ARI Forwarding enable bit check > - using pcie_cap_get_type() instead of simple string comparing (Marcel) > - fix some other comments. > > Gonglei (3): > qdev: Introduce a function to get qbus's parent > pcie: add check for ari capability of pcie devices > pcie: remove confused comments > > hw/core/qdev.c | 9 ++++++++ > hw/pci/pci.c | 4 ++++ > hw/pci/pcie.c | 59 +++++++++++++++++++++++++++++++++++++++++++------- > include/hw/pci/pcie.h | 1 + > include/hw/qdev-core.h | 1 + > 5 files changed, 66 insertions(+), 8 deletions(-) > > -- > 1.7.12.4 >