From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ6Fv-0003PP-8u for qemu-devel@nongnu.org; Tue, 30 Sep 2014 18:50:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XZ6Fr-0005cg-0s for qemu-devel@nongnu.org; Tue, 30 Sep 2014 18:50:51 -0400 Received: from mail-pa0-x230.google.com ([2607:f8b0:400e:c03::230]:37332) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XZ6Fq-0005ay-Og for qemu-devel@nongnu.org; Tue, 30 Sep 2014 18:50:46 -0400 Received: by mail-pa0-f48.google.com with SMTP id eu11so2608630pac.35 for ; Tue, 30 Sep 2014 15:50:44 -0700 (PDT) Date: Wed, 1 Oct 2014 08:50:38 +1000 From: "Edgar E. Iglesias" Message-ID: <20140930225038.GA4029@zapo.iiNet> References: <1412113785-21525-1-git-send-email-greg.bellows@linaro.org> <1412113785-21525-3-git-send-email-greg.bellows@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1412113785-21525-3-git-send-email-greg.bellows@linaro.org> Subject: Re: [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: peter.maydell@linaro.org, Sergey Fedorov , qemu-devel@nongnu.org, aggelerf@ethz.ch, serge.fdrv@gmail.com On Tue, Sep 30, 2014 at 04:49:14PM -0500, Greg Bellows wrote: > From: Fabian Aggeler > > arm_is_secure() function allows to determine CPU security state > if the CPU implements Security Extensions/EL3. > arm_is_secure_below_el3() returns true if CPU is in secure state > below EL3. Hi Greg, > > Signed-off-by: Sergey Fedorov > Signed-off-by: Fabian Aggeler > Signed-off-by: Greg Bellows > --- > target-arm/cpu.h | 38 ++++++++++++++++++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 81fffd2..10afef0 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -753,6 +753,44 @@ static inline int arm_feature(CPUARMState *env, int feature) > return (env->features & (1ULL << feature)) != 0; > } > > + > +/* Return true if exception level below EL3 is in secure state */ > +static inline bool arm_is_secure_below_el3(CPUARMState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + return !(env->cp15.scr_el3 & SCR_NS); > + } else if (arm_feature(env, ARM_FEATURE_EL2)) { > + return false; > + } else { > + /* IMPDEF: QEMU defaults to non-secure */ > + return false; > + } > +#else > + return false; > +#endif > +} arm_is_secure_below_el3() is never called from CONFIG_USER_ONLY code so maybe we could ifdef around the entire function for readability? Or maybe even around both functions and provide a separate static inline bool arm_is_secure(CPUARMState *env) { return false; } for the user_only case. Cheers, Edgar > + > +/* Return true if the processor is in secure state */ > +static inline bool arm_is_secure(CPUARMState *env) > +{ > +#if !defined(CONFIG_USER_ONLY) > + if (arm_feature(env, ARM_FEATURE_EL3)) { > + if (env->aarch64 && extract32(env->pstate, 2, 2) == 3) { > + /* CPU currently in Aarch64 state and EL3 */ > + return true; > + } else if (!env->aarch64 && > + (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) { > + /* CPU currently in Aarch32 state and monitor mode */ > + return true; > + } > + } > + return arm_is_secure_below_el3(env); > +#else > + return false; > +#endif > +} > + > /* Return true if the specified exception level is running in AArch64 state. */ > static inline bool arm_el_is_aa64(CPUARMState *env, int el) > { > -- > 1.8.3.2 >