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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Greg Bellows <greg.bellows@linaro.org>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org,
	aggelerf@ethz.ch, serge.fdrv@gmail.com
Subject: Re: [Qemu-devel] [PATCH v5 22/33] target-arm: add TCR_EL3 and make TTBCR banked
Date: Wed, 1 Oct 2014 09:18:57 +1000	[thread overview]
Message-ID: <20140930231857.GC4029@zapo.iiNet> (raw)
In-Reply-To: <1412113785-21525-23-git-send-email-greg.bellows@linaro.org>

On Tue, Sep 30, 2014 at 04:49:34PM -0500, Greg Bellows wrote:
> From: Fabian Aggeler <aggelerf@ethz.ch>
> 
> Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
> translation functions to use TCR/TTBCR instance depending on CPU state.
> 
> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
> Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
> 
> ----------
> v4 -> v5
> - Changed c2_mask updates to use the TTBCR cpreg bank flag for selcting the
>   secure bank instead of the A32_BANKED_CURRENT macro.  This more accurately
>   chooses the correct bank matching that of the TTBCR being accessed.
> ---
>  target-arm/cpu.h       | 11 ++++++++++-
>  target-arm/helper.c    | 48 +++++++++++++++++++++++++++++++++++-------------
>  target-arm/internals.h |  2 +-
>  3 files changed, 46 insertions(+), 15 deletions(-)
> 
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index c99158e..477c219 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -221,7 +221,16 @@ typedef struct CPUARMState {
>                  uint64_t ttbr1_el1;
>              };
>          };
> -        uint64_t c2_control; /* MMU translation table base control.  */
> +        union { /* MMU translation table base control. */
> +            struct {
> +                uint64_t ttbcr_ns;
> +                uint64_t ttbcr_s;
> +            };
> +            struct {
> +                uint64_t tcr_el1;
> +                uint64_t tcr_el3;
> +            };
> +        };

I was hoping that the aarch64 regs would be arrays (e.g tcr_el[4])...





>          uint32_t c2_mask; /* MMU translation table base selection mask.  */
>          uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
>          uint32_t c2_data; /* MPU data cachable bits.  */
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 2a6a129..bdb76e0 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1678,11 +1678,12 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
>        .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
>        .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
>        .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
> -      .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
> +      .fieldoffset = offsetof(CPUARMState, cp15.tcr_el1) },
>      { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
>        .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
>        .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
> -      .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
> +      .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ttbcr_s),
> +                             offsetoflow32(CPUARMState, cp15.ttbcr_ns) } },
>      /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
>      { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
> @@ -2421,6 +2422,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
>        .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 6, .opc2 = 0,
>        .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
>        .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el3) },
> +    { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 6, .opc2 = 2,
> +      .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
> +      .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
> +      .fieldoffset = offsetof(CPUARMState, cp15.tcr_el3) },
>      { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
>        .type = ARM_CP_NO_MIGRATE,
>        .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
> @@ -4515,13 +4521,13 @@ static bool get_level1_table_address(CPUARMState *env, uint32_t *table,
>       * table registers.
>       */
>      if (address & env->cp15.c2_mask) {
> -        if ((env->cp15.c2_control & TTBCR_PD1)) {
> +        if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD1) {
>              /* Translation table walk disabled for TTBR1 */
>              return false;
>          }
>          *table = A32_BANKED_CURRENT_REG_GET(env, ttbr1) & 0xffffc000;
>      } else {
> -        if ((env->cp15.c2_control & TTBCR_PD0)) {
> +        if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD0) {
>              /* Translation table walk disabled for TTBR0 */
>              return false;
>          }
> @@ -4781,13 +4787,29 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
>      int32_t va_size = 32;
>      int32_t tbi = 0;
>      uint32_t cur_el = arm_current_el(env);
> +    uint64_t tcr;
>  
> -    if (arm_el_is_aa64(env, 1)) {
> +    if (arm_el_is_aa64(env, 3)) {
> +        switch (cur_el) {
> +        case 3:
> +            tcr = env->cp15.tcr_el3;
> +            break;
> +        case 1:
> +        case 0:
> +        default:
> +            tcr = env->cp15.tcr_el1;
> +        }
> +
> +    } else {
> +        tcr = A32_BANKED_CURRENT_REG_GET(env, ttbcr);
> +    }
> +
> +    if (arm_el_is_aa64(env, 1) && (cur_el == 0 || cur_el == 1)) {
>          va_size = 64;
>          if (extract64(address, 55, 1))
> -            tbi = extract64(env->cp15.c2_control, 38, 1);
> +            tbi = extract64(tcr, 38, 1);
>          else
> -            tbi = extract64(env->cp15.c2_control, 37, 1);
> +            tbi = extract64(tcr, 37, 1);
>          tbi *= 8;
>      }
>  
> @@ -4796,12 +4818,12 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
>       * This is a Non-secure PL0/1 stage 1 translation, so controlled by
>       * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
>       */
> -    uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
> +    uint32_t t0sz = extract32(tcr, 0, 6);
>      if (arm_el_is_aa64(env, 1)) {
>          t0sz = MIN(t0sz, 39);
>          t0sz = MAX(t0sz, 16);
>      }
> -    uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
> +    uint32_t t1sz = extract32(tcr, 16, 6);
>      if (arm_el_is_aa64(env, 1)) {
>          t1sz = MIN(t1sz, 39);
>          t1sz = MAX(t1sz, 16);
> @@ -4845,10 +4867,10 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
>          } else {
>              ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr0);
>          }
> -        epd = extract32(env->cp15.c2_control, 7, 1);
> +        epd = extract32(tcr, 7, 1);
>          tsz = t0sz;
>  
> -        tg = extract32(env->cp15.c2_control, 14, 2);
> +        tg = extract32(tcr, 14, 2);
>          if (tg == 1) { /* 64KB pages */
>              granule_sz = 13;
>          }
> @@ -4857,10 +4879,10 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
>          }
>      } else {
>          ttbr = A32_BANKED_CURRENT_REG_GET(env, ttbr1);
> -        epd = extract32(env->cp15.c2_control, 23, 1);
> +        epd = extract32(tcr, 23, 1);
>          tsz = t1sz;
>  
> -        tg = extract32(env->cp15.c2_control, 30, 2);
> +        tg = extract32(tcr, 30, 2);
>          if (tg == 3)  { /* 64KB pages */
>              granule_sz = 13;
>          }
> diff --git a/target-arm/internals.h b/target-arm/internals.h
> index 43a2e7d..dba7766 100644
> --- a/target-arm/internals.h
> +++ b/target-arm/internals.h
> @@ -155,7 +155,7 @@ static inline bool extended_addresses_enabled(CPUARMState *env)
>  {
>      return arm_el_is_aa64(env, 1)
>          || ((arm_feature(env, ARM_FEATURE_LPAE)
> -             && (env->cp15.c2_control & TTBCR_EAE)));
> +             && (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_EAE)));
>  }
>  
>  /* Valid Syndrome Register EC field values */
> -- 
> 1.8.3.2
> 

  reply	other threads:[~2014-09-30 23:19 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-09-30 21:49 [Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 01/33] target-arm: increase arrays of registers R13 & R14 Greg Bellows
2014-10-06 14:48   ` Peter Maydell
2014-10-06 19:21   ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 02/33] target-arm: add arm_is_secure() function Greg Bellows
2014-09-30 22:50   ` Edgar E. Iglesias
2014-10-01 12:53     ` Greg Bellows
2014-10-06 14:56   ` Peter Maydell
2014-10-06 17:57     ` Sergey Fedorov
2014-10-06 18:01       ` Peter Maydell
2014-10-06 19:45     ` Greg Bellows
2014-10-06 20:07       ` Peter Maydell
2014-10-06 20:47         ` Greg Bellows
2014-10-06 21:07           ` Peter Maydell
2014-10-08 19:33             ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 03/33] target-arm: reject switching to monitor mode Greg Bellows
2014-10-06 15:02   ` Peter Maydell
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 04/33] target-arm: rename arm_current_pl to arm_current_el Greg Bellows
2014-09-30 22:56   ` Edgar E. Iglesias
2014-10-01 12:54     ` Greg Bellows
2014-10-06 15:10   ` Peter Maydell
2014-10-06 19:55     ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 05/33] target-arm: make arm_current_pl() return PL3 Greg Bellows
2014-10-01  1:23   ` Sergey Fedorov
2014-10-01 14:31     ` Greg Bellows
2014-10-06 15:34   ` Peter Maydell
2014-10-06 20:53     ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 06/33] target-arm: A32: Emulate the SMC instruction Greg Bellows
2014-10-06 15:46   ` Peter Maydell
2014-10-07  1:56     ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 07/33] target-arm: extend async excp masking Greg Bellows
2014-10-06 15:53   ` Peter Maydell
2014-10-07  3:16     ` Greg Bellows
2014-10-07  7:03       ` Peter Maydell
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 08/33] target-arm: add async excp target_el function Greg Bellows
2014-10-06 16:02   ` Peter Maydell
2014-10-07  3:52     ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 09/33] target-arm: add macros to access banked registers Greg Bellows
2014-10-06 16:09   ` Peter Maydell
2014-10-07  4:02     ` Greg Bellows
2014-10-07  6:54       ` Peter Maydell
2014-10-07 17:49         ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 10/33] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-06 16:13   ` Peter Maydell
2014-10-06 18:10     ` Sergey Fedorov
2014-10-07  4:21       ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 11/33] target-arm: arrayfying fieldoffset for banking Greg Bellows
2014-10-06 16:19   ` Peter Maydell
2014-10-07  5:06     ` Greg Bellows
2014-10-07  7:12       ` Peter Maydell
2014-10-07 21:50         ` Greg Bellows
2014-10-07 22:38           ` Peter Maydell
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 12/33] target-arm: insert Aarch32 cpregs twice into hashtable Greg Bellows
2014-10-06 16:25   ` Peter Maydell
2014-10-07  5:31     ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 13/33] target-arm: move Aarch32 SCR into security reglist Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 14/33] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 15/33] target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 16/33] target-arm: add NSACR register Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 17/33] target-arm: add SDER definition Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 18/33] target-arm: add MVBAR support Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 19/33] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 20/33] target-arm: make CSSELR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 21/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 22/33] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-09-30 23:18   ` Edgar E. Iglesias [this message]
2014-10-01 13:05     ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 23/33] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 24/33] target-arm: make DACR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 25/33] target-arm: make IFSR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 26/33] target-arm: make DFSR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 27/33] target-arm: make IFAR/DFAR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 28/33] target-arm: make PAR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 29/33] target-arm: make VBAR banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 30/33] target-arm: make MAIR0/1 banked Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 31/33] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-01 14:30   ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 32/33] target-arm: add GDB scr register Greg Bellows
2014-10-06 16:27   ` Peter Maydell
2014-10-07  5:09     ` Greg Bellows
2014-09-30 21:49 ` [Qemu-devel] [PATCH v5 33/33] target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows
2014-10-06 16:28   ` Peter Maydell
2014-10-06 16:32 ` [Qemu-devel] [PATCH v5 00/33] target-arm: add Security Extensions for CPUs Peter Maydell

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