From: Thomas Huth <thuth@linux.vnet.ibm.com>
To: Leon Alrae <leon.alrae@imgtec.com>
Cc: qemu-devel@nongnu.org, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v3 02/15] softmmu: provide softmmu access type enum
Date: Fri, 24 Oct 2014 15:59:42 +0200 [thread overview]
Message-ID: <20141024155942.72fa2d22@oc7435384737.ibm.com> (raw)
In-Reply-To: <1414154549-2102-3-git-send-email-leon.alrae@imgtec.com>
On Fri, 24 Oct 2014 13:42:16 +0100
Leon Alrae <leon.alrae@imgtec.com> wrote:
> New MIPS features depend on the access type and enum is more convenient than
> using the numbers directly.
>
> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
> ---
> include/exec/cpu-common.h | 6 ++++++
> softmmu_template.h | 26 ++++++++++++++++----------
> 2 files changed, 22 insertions(+), 10 deletions(-)
>
> diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
> index e3ec4c8..427b851 100644
> --- a/include/exec/cpu-common.h
> +++ b/include/exec/cpu-common.h
> @@ -26,6 +26,12 @@ typedef struct CPUListState {
> FILE *file;
> } CPUListState;
>
> +typedef enum MMUAccessType {
> + MMU_DATA_LOAD = 0,
> + MMU_DATA_STORE = 1,
> + MMU_INST_FETCH = 2
> +} MMUAccessType;
> +
> #if !defined(CONFIG_USER_ONLY)
>
> enum device_endian {
> diff --git a/softmmu_template.h b/softmmu_template.h
> index 88e3390..6b4e615 100644
> --- a/softmmu_template.h
> +++ b/softmmu_template.h
> @@ -67,10 +67,10 @@
> #endif
>
> #ifdef SOFTMMU_CODE_ACCESS
> -#define READ_ACCESS_TYPE 2
> +#define READ_ACCESS_TYPE MMU_INST_FETCH
> #define ADDR_READ addr_code
> #else
> -#define READ_ACCESS_TYPE 0
> +#define READ_ACCESS_TYPE MMU_DATA_LOAD
> #define ADDR_READ addr_read
> #endif
>
> @@ -396,11 +396,12 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
> #ifdef ALIGNED_ONLY
> if ((addr & (DATA_SIZE - 1)) != 0) {
> - cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
> + mmu_idx, retaddr);
> }
> #endif
> if (!VICTIM_TLB_HIT(addr_write)) {
> - tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
> }
> tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> }
> @@ -427,7 +428,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> int i;
> do_unaligned_access:
> #ifdef ALIGNED_ONLY
> - cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
> + mmu_idx, retaddr);
> #endif
> /* XXX: not efficient, but simple */
> /* Note: relies on the fact that tlb_fill() does not remove the
> @@ -446,7 +448,8 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> /* Handle aligned access or unaligned access in the same page. */
> #ifdef ALIGNED_ONLY
> if ((addr & (DATA_SIZE - 1)) != 0) {
> - cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
> + mmu_idx, retaddr);
> }
> #endif
>
> @@ -474,11 +477,12 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
> #ifdef ALIGNED_ONLY
> if ((addr & (DATA_SIZE - 1)) != 0) {
> - cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
> + mmu_idx, retaddr);
> }
> #endif
> if (!VICTIM_TLB_HIT(addr_write)) {
> - tlb_fill(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr);
> }
> tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
> }
> @@ -505,7 +509,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> int i;
> do_unaligned_access:
> #ifdef ALIGNED_ONLY
> - cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
> + mmu_idx, retaddr);
> #endif
> /* XXX: not efficient, but simple */
> /* Note: relies on the fact that tlb_fill() does not remove the
> @@ -524,7 +529,8 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
> /* Handle aligned access or unaligned access in the same page. */
> #ifdef ALIGNED_ONLY
> if ((addr & (DATA_SIZE - 1)) != 0) {
> - cpu_unaligned_access(ENV_GET_CPU(env), addr, 1, mmu_idx, retaddr);
> + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE,
> + mmu_idx, retaddr);
> }
> #endif
>
I very much like the idea to get rid of these "magic" numbers!
Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com>
next prev parent reply other threads:[~2014-10-24 14:00 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-24 12:42 [Qemu-devel] [PATCH v3 00/15] target-mips: add features required in MIPS64R6 Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 01/15] target-mips: add KScratch registers Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 02/15] softmmu: provide softmmu access type enum Leon Alrae
2014-10-24 13:59 ` Thomas Huth [this message]
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 03/15] target-mips: distinguish between data load and instruction fetch Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 04/15] target-mips: add RI and XI fields to TLB entry Leon Alrae
2014-10-24 14:29 ` Yongbok Kim
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 05/15] target-mips: update PageGrain and m{t, f}c0 EntryLo{0, 1} Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 06/15] target-mips: add new Read-Inhibit and Execute-Inhibit exceptions Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 07/15] target-mips: add TLBINV support Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 08/15] target-mips: add BadInstr and BadInstrP support Leon Alrae
2014-10-29 13:55 ` Yongbok Kim
2014-11-01 19:27 ` Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 09/15] target-mips: update cpu_save/cpu_load to support new registers Leon Alrae
2014-10-29 14:02 ` Yongbok Kim
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 10/15] target-mips: add Config5.SBRI Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 11/15] target-mips: implement forbidden slot Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 12/15] target-mips: CP0_Status.CU0 no longer allows the user to access CP0 Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 13/15] target-mips: add restrictions for possible values in registers Leon Alrae
2014-10-29 11:04 ` Yongbok Kim
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 14/15] target-mips: correctly handle access to unimplemented CP0 register Leon Alrae
2014-10-24 12:42 ` [Qemu-devel] [PATCH v3 15/15] target-mips: enable features in MIPS64R6-generic CPU Leon Alrae
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