From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48423) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xj333-00006W-0b for qemu-devel@nongnu.org; Tue, 28 Oct 2014 05:26:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Xj32v-0001EA-59 for qemu-devel@nongnu.org; Tue, 28 Oct 2014 05:26:40 -0400 Received: from e06smtp15.uk.ibm.com ([195.75.94.111]:37204) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xj32u-0001DB-SP for qemu-devel@nongnu.org; Tue, 28 Oct 2014 05:26:33 -0400 Received: from /spool/local by e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 28 Oct 2014 09:26:29 -0000 Received: from b06cxnps3074.portsmouth.uk.ibm.com (d06relay09.portsmouth.uk.ibm.com [9.149.109.194]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id 839051B08067 for ; Tue, 28 Oct 2014 09:26:29 +0000 (GMT) Received: from d06av04.portsmouth.uk.ibm.com (d06av04.portsmouth.uk.ibm.com [9.149.37.216]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id s9S9QQBG14352748 for ; Tue, 28 Oct 2014 09:26:26 GMT Received: from d06av04.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av04.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id s9S9QOCo024540 for ; Tue, 28 Oct 2014 03:26:26 -0600 Date: Tue, 28 Oct 2014 10:26:20 +0100 From: Greg Kurz Message-ID: <20141028102620.7ceba992@bahia.local> In-Reply-To: <1414478281-5956-1-git-send-email-pranavkumar@linaro.org> References: <1414478281-5956-1-git-send-email-pranavkumar@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-arm: Add guest cpu endianness determination for virtio in KVM ARM64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pranavkumar Sawargaonkar Cc: peter.maydell@linaro.org, marc.zyngier@arm.com, patches@apm.com, qemu-devel@nongnu.org, alex.bennee@linaro.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org On Tue, 28 Oct 2014 12:08:01 +0530 Pranavkumar Sawargaonkar wrote: > This patch implements a fucntion pointer virtio_is_big_endian() > from "CPUClass" structure for arm64. > Function aarch64_cpu_virtio_endianness() is added to determine and > returns the guest cpu endianness to virtio. > This is required for running cross endian guests with virtio on ARM64. > > Signed-off-by: Pranavkumar Sawargaonkar > --- > include/hw/virtio/virtio-access.h | 2 ++ > target-arm/cpu64.c | 41 +++++++++++++++++++++++++++++++++++++++ > 2 files changed, 43 insertions(+) > > diff --git a/include/hw/virtio/virtio-access.h b/include/hw/virtio/virtio-access.h > index 46456fd..84fa701 100644 > --- a/include/hw/virtio/virtio-access.h > +++ b/include/hw/virtio/virtio-access.h > @@ -23,6 +23,8 @@ static inline bool virtio_access_is_big_endian(VirtIODevice *vdev) > return virtio_is_big_endian(vdev); > #elif defined(TARGET_WORDS_BIGENDIAN) > return true; > +#elif defined(TARGET_AARCH64) > + return virtio_is_big_endian(vdev); This is code duplication of the TARGET_IS_BIENDIAN case. To be consistent with what was done for ppc64, you should have something like this instead: --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -27,6 +27,7 @@ /* AArch64 definitions */ # define TARGET_LONG_BITS 64 # define ELF_MACHINE EM_AARCH64 +# define TARGET_IS_BIENDIAN 1 #else # define TARGET_LONG_BITS 32 # define ELF_MACHINE EM_ARM > #else > return false; > #endif > diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c > index c30f47e..789f886 100644 > --- a/target-arm/cpu64.c > +++ b/target-arm/cpu64.c > @@ -192,6 +192,43 @@ static void aarch64_cpu_set_pc(CPUState *cs, vaddr value) > } > } > > +#ifndef CONFIG_USER_ONLY > + > +#define KVM_REG_ARM64_SCTLR_EL1 3, 0, 1, 0, 0 > + > +static bool aarch64_cpu_virtio_endianness(CPUState *cs) > +{ > + ARMCPU *cpu = ARM_CPU(cs); > + CPUARMState *env = &cpu->env; > + struct kvm_one_reg reg; > + uint64_t sctlr; > + > + cpu_synchronize_state(cs); > + > + /* Check if we are running 32bit guest or not */ > + if (!is_a64(env)) > + return (env->pstate & CPSR_E) ? 1 : 0; > + > + /* Ideally we do not need to call IOCTL again to read SCTLR_EL1 value. > + * cpu_synchronize_state() should fill the env->cp15.c1_sys > + * to get this value but this path is currently not implemented for arm64. > + * Hence this is a temporary fix. > + */ > + > + reg.id = ARM64_SYS_REG(KVM_REG_ARM64_SCTLR_EL1); > + reg.addr = (uint64_t) &sctlr; > + kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); > + > + if ((env->pstate & 0xf) == PSTATE_MODE_EL0t) > + sctlr &= (1U <<24); > + else > + sctlr &= (1U <<25); > + > + /* If BIG-ENDIAN return 1 */ > + return sctlr ? 1 : 0; > +} > +#endif > + > static void aarch64_cpu_class_init(ObjectClass *oc, void *data) > { > CPUClass *cc = CPU_CLASS(oc); > @@ -203,6 +240,10 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) > cc->gdb_write_register = aarch64_cpu_gdb_write_register; > cc->gdb_num_core_regs = 34; > cc->gdb_core_xml_file = "aarch64-core.xml"; > +#ifndef CONFIG_USER_ONLY > + cc->virtio_is_big_endian = aarch64_cpu_virtio_endianness; > +#endif > + > } > > static void aarch64_cpu_register(const ARMCPUInfo *info)