From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53198) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjGag-0006eE-4E for qemu-devel@nongnu.org; Tue, 28 Oct 2014 19:54:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XjGab-00020N-1t for qemu-devel@nongnu.org; Tue, 28 Oct 2014 19:54:18 -0400 Received: from mailapp01.imgtec.com ([195.59.15.196]:32386) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XjGaa-00020G-PJ for qemu-devel@nongnu.org; Tue, 28 Oct 2014 19:54:12 -0400 Date: Tue, 28 Oct 2014 23:54:08 +0000 From: James Hogan Message-ID: <20141028235408.GC7778@jhogan-linux.le.imgtec.org> References: <1405331763-57126-1-git-send-email-yongbok.kim@imgtec.com> <1405331763-57126-11-git-send-email-yongbok.kim@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <1405331763-57126-11-git-send-email-yongbok.kim@imgtec.com> Subject: Re: [Qemu-devel] [PATCH 10/20] target-mips: add MSA I8 format instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim Cc: cristian.cuna@imgtec.com, leon.alrae@imgtec.com, qemu-devel@nongnu.org, aurelien@aurel32.net On Mon, Jul 14, 2014 at 10:55:53AM +0100, Yongbok Kim wrote: > add MSA I8 format instructions > > Signed-off-by: Yongbok Kim > --- > target-mips/helper.h | 11 ++++ > target-mips/msa_helper.c | 140 ++++++++++++++++++++++++++++++++++++++++++++++ > target-mips/translate.c | 94 ++++++++++++++++++++++++++++++- > 3 files changed, 243 insertions(+), 2 deletions(-) > > diff --git a/target-mips/helper.h b/target-mips/helper.h > index 74ef094..174bc62 100644 > --- a/target-mips/helper.h > +++ b/target-mips/helper.h > @@ -689,3 +689,14 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) > #endif > DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) > DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) > + > +/* MIPS SIMD Architecture */ > + > +DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32) > +DEF_HELPER_4(msa_bmnzi_b, void, env, i32, i32, i32) > +DEF_HELPER_4(msa_bmzi_b, void, env, i32, i32, i32) > +DEF_HELPER_4(msa_bseli_b, void, env, i32, i32, i32) > +DEF_HELPER_4(msa_nori_b, void, env, i32, i32, i32) > +DEF_HELPER_4(msa_ori_b, void, env, i32, i32, i32) > +DEF_HELPER_5(msa_shf_df, void, env, i32, i32, i32, i32) > +DEF_HELPER_4(msa_xori_b, void, env, i32, i32, i32) > diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c > index 5afc9ae..2355809 100644 > --- a/target-mips/msa_helper.c > +++ b/target-mips/msa_helper.c > @@ -194,3 +194,143 @@ static inline void msa_store_wr_elem(CPUMIPSState *env, uint64_t val, > assert(0); > } > } > + > +void helper_msa_andi_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, > + uint32_t i8) > +{ > + void *pwd = &(env->active_fpu.fpr[wd]); > + void *pws = &(env->active_fpu.fpr[ws]); > + ALL_B_ELEMENTS(i, MSA_WRLEN) { > + B(pwd, i) = B(pws, i) & i8; > + } DONE_ALL_ELEMENTS; > + if (env->active_msa.msair & MSAIR_WRP_BIT) { > + env->active_msa.msamodify |= (1 << wd); > + } > +} > + > +void helper_msa_ori_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, > + uint32_t i8) > +{ > + void *pwd = &(env->active_fpu.fpr[wd]); > + void *pws = &(env->active_fpu.fpr[ws]); > + ALL_B_ELEMENTS(i, MSA_WRLEN) { > + B(pwd, i) = B(pws, i) | i8; > + } DONE_ALL_ELEMENTS; > + if (env->active_msa.msair & MSAIR_WRP_BIT) { > + env->active_msa.msamodify |= (1 << wd); > + } > +} > + > +void helper_msa_nori_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, > + uint32_t i8) > +{ > + void *pwd = &(env->active_fpu.fpr[wd]); > + void *pws = &(env->active_fpu.fpr[ws]); > + ALL_B_ELEMENTS(i, MSA_WRLEN) { > + B(pwd, i) = ~(B(pws, i) | i8); > + } DONE_ALL_ELEMENTS; > + if (env->active_msa.msair & MSAIR_WRP_BIT) { > + env->active_msa.msamodify |= (1 << wd); > + } > +} > + > +void helper_msa_xori_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, > + uint32_t i8) > +{ > + void *pwd = &(env->active_fpu.fpr[wd]); > + void *pws = &(env->active_fpu.fpr[ws]); > + ALL_B_ELEMENTS(i, MSA_WRLEN) { > + B(pwd, i) = B(pws, i) ^ i8; > + } DONE_ALL_ELEMENTS; > + if (env->active_msa.msair & MSAIR_WRP_BIT) { > + env->active_msa.msamodify |= (1 << wd); > + } > +} > + > +#define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \ > + dest = UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df) > + > +void helper_msa_bmnzi_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, > + uint32_t i8) > +{ > + void *pwd = &(env->active_fpu.fpr[wd]); > + void *pws = &(env->active_fpu.fpr[ws]); > + ALL_B_ELEMENTS(i, MSA_WRLEN) { > + BIT_MOVE_IF_NOT_ZERO(B(pwd, i), B(pws, i), i8, DF_BYTE); > + } DONE_ALL_ELEMENTS; > + if (env->active_msa.msair & MSAIR_WRP_BIT) { > + env->active_msa.msamodify |= (1 << wd); > + } > +} > + > +#define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \ > + dest = UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df) > + > +void helper_msa_bmzi_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, > + uint32_t i8) > +{ > + void *pwd = &(env->active_fpu.fpr[wd]); > + void *pws = &(env->active_fpu.fpr[ws]); > + ALL_B_ELEMENTS(i, MSA_WRLEN) { > + BIT_MOVE_IF_ZERO(B(pwd, i), B(pws, i), i8, DF_BYTE); > + } DONE_ALL_ELEMENTS; > + if (env->active_msa.msair & MSAIR_WRP_BIT) { > + env->active_msa.msamodify |= (1 << wd); > + } > +} > + > +#define BIT_SELECT(dest, arg1, arg2, df) \ > + dest = UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df) > + > +void helper_msa_bseli_b(CPUMIPSState *env, uint32_t wd, uint32_t ws, > + uint32_t i8) > +{ > + void *pwd = &(env->active_fpu.fpr[wd]); > + void *pws = &(env->active_fpu.fpr[ws]); > + ALL_B_ELEMENTS(i, MSA_WRLEN) { > + BIT_SELECT(B(pwd, i), B(pws, i), i8, DF_BYTE); > + } DONE_ALL_ELEMENTS; > + if (env->active_msa.msair & MSAIR_WRP_BIT) { > + env->active_msa.msamodify |= (1 << wd); > + } > +} I reckon the functions above could all be done easily enough in TCG by repeating i8 up to 64-bits (at translation time) and doing the operations on 64-bit quantities. Out of interest, was there a particular motivation to do it with helpers? In any case, that can always be an experiment for a later patch, and it all looks technically correct. Reviewed-by: James Hogan Cheers James