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Date: Wed, 29 Oct 2014 09:56:44 +0000
From: James Hogan <james.hogan@imgtec.com>
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Subject: Re: [Qemu-devel] [PATCH v2 02/20] target-mips: add MSA exceptions
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To: Yongbok Kim <yongbok.kim@imgtec.com>
Cc: leon.alrae@imgtec.com, qemu-devel@nongnu.org, aurelien@aurel32.net

On Wed, Oct 29, 2014 at 01:41:50AM +0000, Yongbok Kim wrote:
> add MSA exceptions
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>

Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> ---
>  target-mips/helper.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/helper.c b/target-mips/helper.c
> index c92b25c..3a93c20 100644
> --- a/target-mips/helper.c
> +++ b/target-mips/helper.c
> @@ -426,6 +426,8 @@ static const char * const excp_names[EXCP_LAST + 1] = {
>      [EXCP_CACHE] = "cache error",
>      [EXCP_TLBXI] = "TLB execute-inhibit",
>      [EXCP_TLBRI] = "TLB read-inhibit",
> +    [EXCP_MSADIS] = "MSA disabled",
> +    [EXCP_MSAFPE] = "MSA floating point",
>  };
>  
>  target_ulong exception_resume_pc (CPUMIPSState *env)
> @@ -667,6 +669,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
>          cause = 13;
>          update_badinstr = 1;
>          goto set_EPC;
> +    case EXCP_MSAFPE:
> +        cause = 14;
> +        update_badinstr = 1;
> +        goto set_EPC;
>      case EXCP_FPE:
>          cause = 15;
>          update_badinstr = 1;
> @@ -681,6 +687,10 @@ void mips_cpu_do_interrupt(CPUState *cs)
>      case EXCP_TLBXI:
>          cause = 20;
>          goto set_EPC;
> +    case EXCP_MSADIS:
> +        cause = 21;
> +        update_badinstr = 1;
> +        goto set_EPC;
>      case EXCP_MDMX:
>          cause = 22;
>          goto set_EPC;
> -- 
> 1.7.4
> 
>