Re: [Qemu-devel] [PATCH v2 05/20] target-mips: stop translation after ctc1

[James Hogan <james.hogan@imgtec.com>]

On Wed, Oct 29, 2014 at 01:41:53AM +0000, Yongbok Kim wrote:
> stop translation as ctc1 instruction can change hflags
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>

Reviewed-by: James Hogan <james.hogan@imgtec.com>

Cheers
James

> ---
>  target-mips/translate.c |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 9a8f5c9..b388ba5 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -7490,12 +7490,15 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
>          break;
>      case 3:
>          /* XXX: For now we support only a single FPU context. */
> +        save_cpu_state(ctx, 1);
>          {
>              TCGv_i32 fs_tmp = tcg_const_i32(rd);
>  
>              gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
>              tcg_temp_free_i32(fs_tmp);
>          }
> +        /* Stop translation as we may have changed hflags */
> +        ctx->bstate = BS_STOP;
>          break;
>      /* COP2: Not implemented. */
>      case 4:
> @@ -8089,12 +8092,15 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
>          break;
>      case OPC_CTC1:
>          gen_load_gpr(t0, rt);
> +        save_cpu_state(ctx, 1);
>          {
>              TCGv_i32 fs_tmp = tcg_const_i32(fs);
>  
>              gen_helper_0e2i(ctc1, t0, fs_tmp, rt);
>              tcg_temp_free_i32(fs_tmp);
>          }
> +        /* Stop translation as we may have changed hflags */
> +        ctx->bstate = BS_STOP;
>          opn = "ctc1";
>          break;
>  #if defined(TARGET_MIPS64)
> -- 
> 1.7.4
> 
>