From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54100) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Xlumf-00086z-TY for qemu-devel@nongnu.org; Wed, 05 Nov 2014 02:13:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1XlumW-0001Xm-Qn for qemu-devel@nongnu.org; Wed, 05 Nov 2014 02:13:37 -0500 Received: from e37.co.us.ibm.com ([32.97.110.158]:51384) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1XlumW-0001XZ-Fo for qemu-devel@nongnu.org; Wed, 05 Nov 2014 02:13:28 -0500 Received: from /spool/local by e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 5 Nov 2014 00:13:27 -0700 From: Aravinda Prasad Date: Wed, 05 Nov 2014 12:43:15 +0530 Message-ID: <20141105071315.26196.68104.stgit@aravindap> In-Reply-To: <20141105071019.26196.93729.stgit@aravindap> References: <20141105071019.26196.93729.stgit@aravindap> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH v3 4/4] target-ppc: Handle ibm, nmi-register RTAS call List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: aik@au1.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Cc: benh@au1.ibm.com, paulus@samba.org This patch adds FWNMI support in qemu for powerKVM guests by handling the ibm,nmi-register rtas call. Whenever OS issues ibm,nmi-register RTAS call, the machine check notification address is saved and the machine check interrupt vector 0x200 is patched to issue a private hcall. This patch also handles the cases when multi-processors experience machine check at or about the same time. As per PAPR, subsequent processors serialize waiting for the first processor to issue the ibm,nmi-interlock call. The second processor retries if the first processor which received a machine check is still reading the error log and is yet to issue ibm,nmi-interlock call. Signed-off-by: Aravinda Prasad --- hw/ppc/spapr_hcall.c | 16 +++++++ hw/ppc/spapr_rtas.c | 93 +++++++++++++++++++++++++++++++++++++++ include/hw/ppc/spapr.h | 17 +++++++ pc-bios/spapr-rtas/spapr-rtas.S | 38 ++++++++++++++++ 4 files changed, 163 insertions(+), 1 deletion(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 8f16160..eceb5e5 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -97,6 +97,9 @@ struct rtas_mc_log { struct rtas_error_log err_log; }; +/* Whether machine check handling is in progress by any CPU */ +bool mc_in_progress; + static void do_spr_sync(void *arg) { struct SPRSyncState *s = arg; @@ -678,6 +681,19 @@ static target_ulong h_report_mc_err(PowerPCCPU *cpu, sPAPREnvironment *spapr, cpu_synchronize_state(CPU(ppc_env_get_cpu(env))); /* + * Only one VCPU can process machine check NMI at a time. Hence + * set the lock mc_in_progress. Once the VCPU finishes processing + * NMI, it executes ibm,nmi-interlock and mc_in_progress is unset + * in ibm,nmi-interlock handler. Meanwhile if other VCPUs encounter + * NMI we return 0 asking the VCPU to retry h_report_mc_err + */ + if (mc_in_progress == 1) { + return 0; + } + + mc_in_progress = 1; + + /* * We save the original r3 register in SPRG2 in 0x200 vector, * which is patched during call to ibm.nmi-register. Original * r3 is required to be included in error log diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 2ec2a8e..71c7662 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -36,6 +36,9 @@ #include +#define BRANCH_INST_MASK 0xFC000000 +extern bool mc_in_progress; + static void rtas_display_character(PowerPCCPU *cpu, sPAPREnvironment *spapr, uint32_t token, uint32_t nargs, target_ulong args, @@ -290,6 +293,90 @@ static void rtas_ibm_os_term(PowerPCCPU *cpu, rtas_st(rets, 0, ret); } +static void rtas_ibm_nmi_register(PowerPCCPU *cpu, + sPAPREnvironment *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, + uint32_t nret, target_ulong rets) +{ + int i; + uint32_t ori_inst = 0x60630000; + uint32_t branch_inst = 0x48000002; + target_ulong guest_machine_check_addr; + uint32_t trampoline[TRAMPOLINE_INSTS]; + int total_inst = sizeof(trampoline) / sizeof(uint32_t); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + + /* Store the system reset and machine check address */ + guest_machine_check_addr = rtas_ld(args, 1); + + /* + * Read the trampoline instructions from RTAS Blob and patch + * the KVMPPC_H_REPORT_MC_ERR hcall number and the guest + * machine check address before copying to 0x200 vector + */ + cpu_physical_memory_read(spapr->rtas_addr + RTAS_TRAMPOLINE_OFFSET, + trampoline, sizeof(trampoline)); + + /* Safety Check */ + QEMU_BUILD_BUG_ON(sizeof(trampoline) > MC_INTERRUPT_VECTOR_SIZE); + + /* Update the KVMPPC_H_REPORT_MC_ERR value in trampoline */ + ori_inst |= KVMPPC_H_REPORT_MC_ERR; + memcpy(&trampoline[TRAMPOLINE_ORI_INST_INDEX], &ori_inst, + sizeof(ori_inst)); + + /* + * Sanity check guest_machine_check_addr to prevent clobbering + * operator value in branch instruction + */ + if (guest_machine_check_addr & BRANCH_INST_MASK) { + fprintf(stderr, "Unable to register ibm,nmi_register: " + "Invalid machine check handler address\n"); + rtas_st(rets, 0, RTAS_OUT_NOT_SUPPORTED); + return; + } + + /* + * Update the branch instruction in trampoline + * with the absolute machine check address requested by OS. + */ + branch_inst |= guest_machine_check_addr; + memcpy(&trampoline[TRAMPOLINE_BR_INST_INDEX], &branch_inst, + sizeof(branch_inst)); + + /* Handle all Host/Guest LE/BE combinations */ + if ((*pcc->interrupts_big_endian)(cpu)) { + for (i = 0; i < total_inst; i++) { + trampoline[i] = cpu_to_be32(trampoline[i]); + } + } else { + for (i = 0; i < total_inst; i++) { + trampoline[i] = cpu_to_le32(trampoline[i]); + } + } + + /* Patch 0x200 NMI interrupt vector memory area of guest */ + cpu_physical_memory_write(MC_INTERRUPT_VECTOR, trampoline, + sizeof(trampoline)); + + rtas_st(rets, 0, RTAS_OUT_SUCCESS); +} + +static void rtas_ibm_nmi_interlock(PowerPCCPU *cpu, + sPAPREnvironment *spapr, + uint32_t token, uint32_t nargs, + target_ulong args, + uint32_t nret, target_ulong rets) +{ + /* + * VCPU issuing ibm,nmi-interlock is done with NMI handling, + * hence unset mc_in_progress. + */ + mc_in_progress = 0; + rtas_st(rets, 0, RTAS_OUT_SUCCESS); +} + static struct rtas_call { const char *name; spapr_rtas_fn fn; @@ -419,6 +506,12 @@ static void core_rtas_register_types(void) rtas_ibm_set_system_parameter); spapr_rtas_register(RTAS_IBM_OS_TERM, "ibm,os-term", rtas_ibm_os_term); + spapr_rtas_register(RTAS_IBM_NMI_REGISTER, + "ibm,nmi-register", + rtas_ibm_nmi_register); + spapr_rtas_register(RTAS_IBM_NMI_INTERLOCK, + "ibm,nmi-interlock", + rtas_ibm_nmi_interlock); } type_init(core_rtas_register_types) diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index a2d67e9..98d0a6c 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -384,8 +384,10 @@ int spapr_allocate_irq_block(int num, bool lsi, bool msi); #define RTAS_GET_SENSOR_STATE (RTAS_TOKEN_BASE + 0x1D) #define RTAS_IBM_CONFIGURE_CONNECTOR (RTAS_TOKEN_BASE + 0x1E) #define RTAS_IBM_OS_TERM (RTAS_TOKEN_BASE + 0x1F) +#define RTAS_IBM_NMI_REGISTER (RTAS_TOKEN_BASE + 0x20) +#define RTAS_IBM_NMI_INTERLOCK (RTAS_TOKEN_BASE + 0x21) -#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x20) +#define RTAS_TOKEN_MAX (RTAS_TOKEN_BASE + 0x22) /* RTAS ibm,get-system-parameter token values */ #define RTAS_SYSPARM_SPLPAR_CHARACTERISTICS 20 @@ -488,4 +490,17 @@ int spapr_tcet_dma_dt(void *fdt, int node_off, const char *propname, #define RTAS_TRAMPOLINE_OFFSET 0x200 #define RTAS_ERRLOG_OFFSET 0x800 +/* Machine Check Trampoline related macros + * + * These macros should co-relate to the code we + * have in pc-bios/spapr-rtas/spapr-rtas.S + */ +#define TRAMPOLINE_INSTS 17 +#define TRAMPOLINE_ORI_INST_INDEX 2 +#define TRAMPOLINE_BR_INST_INDEX 15 + +/* Machine Check Interrupt related macros */ +#define MC_INTERRUPT_VECTOR 0x200 +#define MC_INTERRUPT_VECTOR_SIZE 0x100 + #endif /* !defined (__HW_SPAPR_H__) */ diff --git a/pc-bios/spapr-rtas/spapr-rtas.S b/pc-bios/spapr-rtas/spapr-rtas.S index 903bec2..c315332 100644 --- a/pc-bios/spapr-rtas/spapr-rtas.S +++ b/pc-bios/spapr-rtas/spapr-rtas.S @@ -35,3 +35,41 @@ _start: ori 3,3,KVMPPC_H_RTAS@l sc 1 blr + . = 0x200 + /* + * Trampoline saves r3 in sprg2 and issues private hcall + * to request qemu to build error log. QEMU builds the + * error log, copies to rtas-blob and returns the address. + * The initial 16 bytes in return adress consist of saved + * srr0 and srr1 which we restore and pass on the actual error + * log address to OS handled mcachine check notification + * routine + * + * All the below instructions are copied to interrupt vector + * 0x200 at the time of handling ibm,nmi-register rtas call. + */ + mtsprg 2,3 + li 3,0 + /* + * ori r3,r3,KVMPPC_H_REPORT_MC_ERR. The KVMPPC_H_REPORT_MC_ERR + * value is patched below + */ +1: ori 3,3,0 + sc 1 /* Issue H_CALL */ + cmpdi cr0,3,0 + beq cr0,1b /* retry KVMPPC_H_REPORT_MC_ERR */ + mtsprg 2,4 + ld 4,0(3) + mtsrr0 4 /* Restore srr0 */ + ld 4,8(3) + mtsrr1 4 /* Restore srr1 */ + ld 4,16(3) + mtcrf 0,4 /* Restore cr */ + addi 3,3,24 + mfsprg 4,2 + /* + * Branch to address registered by OS. The branch address is + * patched in the ibm,nmi-register rtas call. + */ + ba 0x0 + b .