From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48472) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0XvD-0004a7-Bf for qemu-devel@nongnu.org; Mon, 15 Dec 2014 10:51:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Y0Xv7-0008Me-20 for qemu-devel@nongnu.org; Mon, 15 Dec 2014 10:50:55 -0500 Received: from mx1.redhat.com ([209.132.183.28]:47772) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Y0Xv6-0008MT-PC for qemu-devel@nongnu.org; Mon, 15 Dec 2014 10:50:48 -0500 Date: Mon, 15 Dec 2014 15:50:40 +0000 From: "Dr. David Alan Gilbert" Message-ID: <20141215155040.GI5502@work-vm> References: <1418388243-1886-1-git-send-email-pbonzini@redhat.com> <1418388243-1886-4-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1418388243-1886-4-git-send-email-pbonzini@redhat.com> Subject: Re: [Qemu-devel] [PATCH v3 3/4] serial: update LSR on enabling/disabling FIFOs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: imammedo@redhat.com, andrey@xdel.ru, qemu-devel@nongnu.org, batuzovk@ispras.ru * Paolo Bonzini (pbonzini@redhat.com) wrote: > When the transmit FIFO is emptied or enabled, the transmitter > hold register is empty. When it is disabled, it is also emptied and > in addition the previous contents of the transmitter hold register > are discarded. In either case, the THRE bit in LSR must be set and > THRI raised. > > When the receive FIFO is emptied or enabled, the data ready and break > bits must be cleared in LSR. Likewise when the receive FIFO is disabled. > > Signed-off-by: Paolo Bonzini > --- > hw/char/serial.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/hw/char/serial.c b/hw/char/serial.c > index 4bce268..0a6747c 100644 > --- a/hw/char/serial.c > +++ b/hw/char/serial.c > @@ -377,12 +377,15 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val, > /* FIFO clear */ > > if (val & UART_FCR_RFR) { > + s->lsr &= ~(UART_LSR_DR | UART_LSR_BI); > timer_del(s->fifo_timeout_timer); > s->timeout_ipending = 0; > fifo8_reset(&s->recv_fifo); > } > > if (val & UART_FCR_XFR) { > + s->lsr |= UART_LSR_THRE; > + s->thr_ipending = 1; > fifo8_reset(&s->xmit_fifo); > } Doesn't that break the assertion you added in patch 2? i.e. if I write a character, but it can't be sent, so it's added to the tsr_retry, but before the callback I set FCR_XFR, and that now sets LSR_THRE, then the callback triggers and it hits the assert? Dave > > -- > 1.8.3.1 > > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK