From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49702) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YB3gH-00038Q-Fv for qemu-devel@nongnu.org; Tue, 13 Jan 2015 10:46:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YB3gC-0002iZ-CS for qemu-devel@nongnu.org; Tue, 13 Jan 2015 10:46:57 -0500 Received: from mx1.redhat.com ([209.132.183.28]:37494) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YB3gC-0002i3-5N for qemu-devel@nongnu.org; Tue, 13 Jan 2015 10:46:52 -0500 Date: Tue, 13 Jan 2015 16:46:45 +0100 From: Andrew Jones Message-ID: <20150113154644.GA19672@hawk.usersys.redhat.com> References: <1420823193-17609-1-git-send-email-drjones@redhat.com> <1421066807-4652-1-git-send-email-drjones@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1421066807-4652-1-git-send-email-drjones@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2] tcg-arm: more instruction execution control List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org On Mon, Jan 12, 2015 at 01:46:47PM +0100, Andrew Jones wrote: > Cleanup XN/PXN handling in get_phys_addr_lpae, and implement all but > EL2 support of the following ARMv8 sections > > D4.5.1 Memory access control: Access permissions for instruction > execution > G4.7.2 Execute-never restrictions on instruction fetching > > G4.7.2 matches the ARMv7 section B3.7.2 when long-descriptors are used. > > Signed-off-by: Andrew Jones > While confirming the documentation wasn't wrong (it wasn't), I see I missed another issue with qemu's instruction execution control. For AArch64, EL0 can execute code even if it doesn't have R/W access, i.e. AP[1]=0. To make this fix more clear I've done it in a separate patch, and then rebased this patch on that. Thus, please drop this patch, as I'll send a 2-patch patch series now that replaces it. drew