From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Richard Henderson <rth@twiddle.net>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Sergey Fedorov <serge.fdrv@gmail.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Fabian Aggeler <aggelerf@ethz.ch>,
Greg Bellows <greg.bellows@linaro.org>
Subject: Re: [Qemu-devel] [PATCH v7 05/32] target-arm: make arm_current_el() return EL3
Date: Tue, 20 Jan 2015 08:54:16 +1000 [thread overview]
Message-ID: <20150119225416.GB24013@toto> (raw)
In-Reply-To: <54BD5B6B.6090708@twiddle.net>
On Mon, Jan 19, 2015 at 11:30:51AM -0800, Richard Henderson wrote:
> On 01/19/2015 11:00 AM, Peter Maydell wrote:
> > Alternatively (better!), for a lot of the tlb_flush()es triggered
> > by target-arm code we could be more precise about the affected
> > mmu_idx values, since the common case is going to be
> > "NS EL1 did something that needs a TLB flush", and by definition
> > that can't affect TLB entries for EL2, EL3 or S-EL1/EL0.
> >
> > So I think my preference would be to use 7 mmu indexes,
> > and add a tlb_flush_mmuidx() function. (Assuming I'm
> > not missing anything that makes that not workable...)
>
> That new interface does seem very reasonable.
>
> As to whether you've missed something in the ARM semantics,
> I guess we'll find out. ;-)
>
Sounds like a good option to me too.
Cheers,
Edgar
next prev parent reply other threads:[~2015-01-19 22:57 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-21 16:55 [Qemu-devel] [PATCH v7 00/32] target-arm: add Security Extensions for CPUs Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 01/32] target-arm: increase arrays of registers R13 & R14 Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 02/32] target-arm: add arm_is_secure() function Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 03/32] target-arm: reject switching to monitor mode Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 04/32] target-arm: rename arm_current_pl to arm_current_el Greg Bellows
2014-10-23 14:53 ` Peter Maydell
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 05/32] target-arm: make arm_current_el() return EL3 Greg Bellows
2015-01-16 18:36 ` Peter Maydell
2015-01-19 13:22 ` Peter Maydell
2015-01-19 17:44 ` Richard Henderson
2015-01-19 19:00 ` Peter Maydell
2015-01-19 19:30 ` Richard Henderson
2015-01-19 22:54 ` Edgar E. Iglesias [this message]
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 06/32] target-arm: A32: Emulate the SMC instruction Greg Bellows
2014-10-23 14:06 ` Peter Maydell
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 07/32] target-arm: extend async excp masking Greg Bellows
2014-10-24 16:25 ` Peter Maydell
2014-10-24 22:43 ` Greg Bellows
2014-10-26 22:30 ` Peter Maydell
2014-10-27 11:57 ` Peter Maydell
2014-10-27 15:59 ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 08/32] target-arm: add async excp target_el function Greg Bellows
2014-10-24 16:26 ` Peter Maydell
2014-10-28 14:50 ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 09/32] target-arm: add banked register accessors Greg Bellows
2014-10-24 16:37 ` Peter Maydell
2014-10-28 18:42 ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 10/32] target-arm: add non-secure Translation Block flag Greg Bellows
2014-10-24 16:40 ` Peter Maydell
2014-10-28 15:21 ` Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 11/32] target-arm: add CPREG secure state support Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 12/32] target-arm: add secure state bit to CPREG hash Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 13/32] target-arm: insert AArch32 cpregs twice into hashtable Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 14/32] target-arm: move AArch32 SCR into security reglist Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 15/32] target-arm: implement IRQ/FIQ routing to Monitor mode Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 16/32] target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 17/32] target-arm: add NSACR register Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 18/32] target-arm: add SDER definition Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 19/32] target-arm: add MVBAR support Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 20/32] target-arm: add SCTLR_EL3 and make SCTLR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 21/32] target-arm: make CSSELR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 22/32] target-arm: add TTBR0_EL3 and make TTBR0/1 banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 23/32] target-arm: add TCR_EL3 and make TTBCR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 24/32] target-arm: make c2_mask and c2_base_mask banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 25/32] target-arm: make DACR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 26/32] target-arm: make IFSR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 27/32] target-arm: make DFSR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 28/32] target-arm: make IFAR/DFAR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 29/32] target-arm: make PAR banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 30/32] target-arm: make c13 cp regs banked (FCSEIDR, ...) Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 31/32] target-arm: make MAIR0/1 banked Greg Bellows
2014-10-21 16:55 ` [Qemu-devel] [PATCH v7 32/32] target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows
2014-10-23 14:19 ` [Qemu-devel] [PATCH v7 00/32] target-arm: add Security Extensions for CPUs Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20150119225416.GB24013@toto \
--to=edgar.iglesias@gmail.com \
--cc=aggelerf@ethz.ch \
--cc=greg.bellows@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=rth@twiddle.net \
--cc=serge.fdrv@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).