From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:50718) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDtlc-0007Tg-TU for qemu-devel@nongnu.org; Wed, 21 Jan 2015 06:48:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YDtlX-0005Il-F0 for qemu-devel@nongnu.org; Wed, 21 Jan 2015 06:48:12 -0500 Received: from mx1.redhat.com ([209.132.183.28]:49357) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YDtlX-0005Ib-6K for qemu-devel@nongnu.org; Wed, 21 Jan 2015 06:48:07 -0500 Date: Wed, 21 Jan 2015 13:48:00 +0200 From: "Michael S. Tsirkin" Message-ID: <20150121114800.GA15439@redhat.com> References: <094404b0fbe3a2f7d49a3c30f4d128666b33b36b.1418264106.git.hutao@cn.fujitsu.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <094404b0fbe3a2f7d49a3c30f4d128666b33b36b.1418264106.git.hutao@cn.fujitsu.com> Subject: Re: [Qemu-devel] [PATCH v3 1/6] pci: reorganize QEMU_PCI_CAP_* List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Hu Tao Cc: qemu-devel@nongnu.org, Marcel Apfelbaum On Thu, Dec 11, 2014 at 10:20:23AM +0800, Hu Tao wrote: > This makes code more readable. > > Signed-off-by: Hu Tao > Reviewed-by: Marcel Apfelbaum > --- > include/hw/pci/pci.h | 39 ++++++++++++++++++++------------------- > 1 file changed, 20 insertions(+), 19 deletions(-) > > diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > index c352c7b..b18759a 100644 > --- a/include/hw/pci/pci.h > +++ b/include/hw/pci/pci.h > @@ -142,25 +142,26 @@ enum { > > /* Bits in cap_present field. */ > enum { > - QEMU_PCI_CAP_MSI = 0x1, > - QEMU_PCI_CAP_MSIX = 0x2, > - QEMU_PCI_CAP_EXPRESS = 0x4, > - > - /* multifunction capable device */ > -#define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3 > - QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), > - > - /* command register SERR bit enabled */ > -#define QEMU_PCI_CAP_SERR_BITNR 4 > - QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), > - /* Standard hot plug controller. */ > -#define QEMU_PCI_SHPC_BITNR 5 > - QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), > -#define QEMU_PCI_SLOTID_BITNR 6 > - QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), > - /* PCI Express capability - Power Controller Present */ > -#define QEMU_PCIE_SLTCAP_PCP_BITNR 7 > - QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), > + QEMU_PCI_CAP_MSI_BITNR = 0, > + QEMU_PCI_CAP_MSIX_BITNR, > + QEMU_PCI_CAP_EXPRESS_BITNR, > + QEMU_PCI_CAP_MULTIFUNCTION_BITNR, /* multifunction capable device */ > + QEMU_PCI_CAP_SERR_BITNR, /* command register SERR bit enabled */ > + QEMU_PCI_SHPC_BITNR, /* Standard hot plug controller */ > + QEMU_PCI_SLOTID_BITNR, > + QEMU_PCIE_SLTCAP_PCP_BITNR, /* PCIE Slot - Power Controller >+ Present */ Pls shorten so it fits on one line: /* PCIE Slot - Power Controller Present */ > +}; > + > +enum { > + QEMU_PCI_CAP_MSI = (1 << QEMU_PCI_CAP_MSI_BITNR), > + QEMU_PCI_CAP_MSIX = (1 << QEMU_PCI_CAP_MSIX_BITNR), > + QEMU_PCI_CAP_EXPRESS = (1 << QEMU_PCI_CAP_EXPRESS_BITNR), > + QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR), > + QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR), > + QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR), > + QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR), > + QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR), > }; > > #define TYPE_PCI_DEVICE "pci-device" > -- > 1.9.3