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From: "Michael S. Tsirkin" <mst@redhat.com>
To: Hu Tao <hutao@cn.fujitsu.com>
Cc: qemu-devel@nongnu.org, Marcel Apfelbaum <marcel.a@redhat.com>
Subject: Re: [Qemu-devel] [PATCH v3 5/6] pci: remove the limit parameter of pci_host_config_write_common
Date: Wed, 21 Jan 2015 13:57:20 +0200	[thread overview]
Message-ID: <20150121115720.GE15439@redhat.com> (raw)
In-Reply-To: <123a9bd4cbf76a6884ef01d6533f7572bf0b3dff.1418264106.git.hutao@cn.fujitsu.com>

On Thu, Dec 11, 2014 at 10:20:27AM +0800, Hu Tao wrote:
> Since the limit parameter is always set to the size of pci device's
> configuration space, and we can determine the size from the type of pci
> device.

Same comment.

> Signed-off-by: Hu Tao <hutao@cn.fujitsu.com>
> ---
>  hw/pci/pci_host.c         | 13 ++++++++++---
>  hw/pci/pcie_host.c        |  9 +--------
>  hw/ppc/spapr_pci.c        |  3 +--
>  include/hw/pci/pci_host.h |  2 +-
>  4 files changed, 13 insertions(+), 14 deletions(-)
> 
> diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c
> index 2b11551..4a59b0e 100644
> --- a/hw/pci/pci_host.c
> +++ b/hw/pci/pci_host.c
> @@ -49,8 +49,16 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
>  }
>  
>  void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
> -                                  uint32_t limit, uint32_t val, uint32_t len)
> +                                  uint32_t val, uint32_t len)
>  {
> +    uint32_t limit = pci_config_size(pci_dev);
> +
> +    if (limit <= addr) {
> +        /* conventional pci device can be behind pcie-to-pci bridge.
> +           256 <= addr < 4K has no effects. */
> +        return;
> +    }
> +
>      assert(len <= 4);
>      trace_pci_cfg_write(pci_dev->name, PCI_SLOT(pci_dev->devfn),
>                          PCI_FUNC(pci_dev->devfn), addr, val);
> @@ -89,8 +97,7 @@ void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
>  
>      PCI_DPRINTF("%s: %s: addr=%02" PRIx32 " val=%08" PRIx32 " len=%d\n",
>                  __func__, pci_dev->name, config_addr, val, len);
> -    pci_host_config_write_common(pci_dev, config_addr, PCI_CONFIG_SPACE_SIZE,
> -                                 val, len);
> +    pci_host_config_write_common(pci_dev, config_addr, val, len);
>  }
>  
>  uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
> diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
> index cf8587b..e3a2a80 100644
> --- a/hw/pci/pcie_host.c
> +++ b/hw/pci/pcie_host.c
> @@ -39,19 +39,12 @@ static void pcie_mmcfg_data_write(void *opaque, hwaddr mmcfg_addr,
>      PCIBus *s = e->pci.bus;
>      PCIDevice *pci_dev = pcie_dev_find_by_mmcfg_addr(s, mmcfg_addr);
>      uint32_t addr;
> -    uint32_t limit;
>  
>      if (!pci_dev) {
>          return;
>      }
>      addr = PCIE_MMCFG_CONFOFFSET(mmcfg_addr);
> -    limit = pci_config_size(pci_dev);
> -    if (limit <= addr) {
> -        /* conventional pci device can be behind pcie-to-pci bridge.
> -           256 <= addr < 4K has no effects. */
> -        return;
> -    }
> -    pci_host_config_write_common(pci_dev, addr, limit, val, len);
> +    pci_host_config_write_common(pci_dev, addr, val, len);
>  }
>  
>  static uint64_t pcie_mmcfg_data_read(void *opaque,
> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
> index 59c6608..8c566dd 100644
> --- a/hw/ppc/spapr_pci.c
> +++ b/hw/ppc/spapr_pci.c
> @@ -171,8 +171,7 @@ static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid,
>          return;
>      }
>  
> -    pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev),
> -                                 val, size);
> +    pci_host_config_write_common(pci_dev, addr, val, size);
>  
>      rtas_st(rets, 0, RTAS_OUT_SUCCESS);
>  }
> diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h
> index 72a1b8b..67e007f 100644
> --- a/include/hw/pci/pci_host.h
> +++ b/include/hw/pci/pci_host.h
> @@ -63,7 +63,7 @@ typedef struct PCIHostBridgeClass {
>  
>  /* common internal helpers for PCI/PCIe hosts, cut off overflows */
>  void pci_host_config_write_common(PCIDevice *pci_dev, uint32_t addr,
> -                                  uint32_t limit, uint32_t val, uint32_t len);
> +                                  uint32_t val, uint32_t len);
>  uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
>                                       uint32_t len);
>  
> -- 
> 1.9.3

  reply	other threads:[~2015-01-21 11:57 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-11  2:20 [Qemu-devel] [PATCH v3 0/6] Some PCI related cleanup patches Hu Tao
2014-12-11  2:20 ` [Qemu-devel] [PATCH v3 1/6] pci: reorganize QEMU_PCI_CAP_* Hu Tao
2015-01-21 11:48   ` Michael S. Tsirkin
2014-12-11  2:20 ` [Qemu-devel] [PATCH v3 2/6] pci: introduce pci_host_config_enabled() Hu Tao
2015-01-21 11:50   ` Michael S. Tsirkin
2014-12-11  2:20 ` [Qemu-devel] [PATCH v3 3/6] pci: define PCI_HOST_BRIDGE_CONFIG_ADDR and PCI_HOST_BRIDGE_CONFIG_DATA Hu Tao
2015-01-21 11:54   ` Michael S. Tsirkin
2015-01-27 11:18   ` Michael S. Tsirkin
2014-12-11  2:20 ` [Qemu-devel] [PATCH v3 4/6] pci: remove the limit parameter of pci_host_config_read_common Hu Tao
2015-01-21 11:57   ` Michael S. Tsirkin
2015-01-27 11:20   ` Michael S. Tsirkin
2014-12-11  2:20 ` [Qemu-devel] [PATCH v3 5/6] pci: remove the limit parameter of pci_host_config_write_common Hu Tao
2015-01-21 11:57   ` Michael S. Tsirkin [this message]
2014-12-11  2:20 ` [Qemu-devel] [PATCH v3 6/6] pci: introduce PCI_DEVFN_AUTO Hu Tao
2014-12-11  2:46   ` Hu Tao
2015-01-21 12:00   ` Michael S. Tsirkin
2015-01-27  6:42     ` Hu Tao
2014-12-11  2:50 ` [Qemu-devel] [PATCH v3 RESEND " Hu Tao
2015-01-21  6:41 ` [Qemu-devel] [PATCH v3 0/6] Some PCI related cleanup patches Hu Tao
2015-01-21 12:00   ` Michael S. Tsirkin
2015-01-27  6:44     ` Hu Tao

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