From: Christoffer Dall <christoffer.dall@linaro.org>
To: "Alex Bennée" <alex.bennee@linaro.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
kvm@vger.kernel.org, marc.zyngier@arm.com, qemu-devel@nongnu.org,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [Qemu-devel] [PATCH 5/6] target-arm/kvm64: fix save/restore of SPSR regs
Date: Mon, 2 Mar 2015 09:22:12 -0800 [thread overview]
Message-ID: <20150302172212.GB10137@lvm> (raw)
In-Reply-To: <1424880159-29348-7-git-send-email-alex.bennee@linaro.org>
Hi Alex,
Seems like you accidentally sent out two copies of this patch, hopefully
I'm reviewing the right one...
On Wed, Feb 25, 2015 at 04:02:38PM +0000, Alex Bennée wrote:
> From: Christoffer Dall <christoffer.dall@linaro.org>
>
> The current code was negatively indexing the cpu state array and not
> synchronizing banked spsr register state with the current mode's spsr
> state, causing occasional failures with migration.
>
> Some munging is done to take care of the aarch64 mapping and also to
> ensure the most current value of the spsr is updated to the banked
> registers (relevant for KVM<->TCG migration).
>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
>
> ---
> v2 (ajb)
> - minor tweaks and clarifications
>
> diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c
> index c60e989..1e36b0a 100644
> --- a/target-arm/kvm64.c
> +++ b/target-arm/kvm64.c
> @@ -140,6 +140,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
> uint64_t val;
> int i;
> int ret;
> + unsigned int el;
>
> ARMCPU *cpu = ARM_CPU(cs);
> CPUARMState *env = &cpu->env;
> @@ -206,9 +207,25 @@ int kvm_arch_put_registers(CPUState *cs, int level)
> return ret;
> }
>
> + /* Saved Program State Registers
> + *
> + * Before we restore from the banked_spsr[] array we need to
> + * ensure that any modifications to env->spsr are correctly
> + * reflected and map aarch64 exception levels if required.
> + */
> + el = arm_current_el(env);
> + if (is_a64(env) && el > 0) {
> + g_assert(el == 1);
> + /* KVM maps KVM_SPSR_SVC to KVM_SPSR_EL1 for aarch64 */
> + env->banked_spsr[1] = env->banked_spsr[0];
> + env->banked_spsr[aarch64_banked_spsr_index(el)] = env->spsr;
> + } else {
> + env->banked_spsr[el] = env->spsr;
is this valid if (is_a64(env) && el == 0)) ? I thought that if you're
in el == 0, then env->banked_spsr[x] is the most up-to-date one, not
env->spsr ?
for !is_a64(env) this looks wrong, because of the same as above if el ==
0, but also because I think you need
bank_number(env->uncached_cpsr & CPSR_M) to index into the array.
> + }
> +
> for (i = 0; i < KVM_NR_SPSR; i++) {
> reg.id = AARCH64_CORE_REG(spsr[i]);
> - reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
> + reg.addr = (uintptr_t) &env->banked_spsr[i+1];
> ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
> if (ret) {
> return ret;
> @@ -253,6 +270,7 @@ int kvm_arch_get_registers(CPUState *cs)
> struct kvm_one_reg reg;
> uint64_t val;
> uint32_t fpr;
> + unsigned int el;
> int i;
> int ret;
>
> @@ -325,15 +343,32 @@ int kvm_arch_get_registers(CPUState *cs)
> return ret;
> }
>
> + /* Fetch the SPSR registers
> + *
> + * KVM has an array of state indexed for all the possible aarch32
> + * privilage levels. Although not all are valid at all points
> + * there are some transitions possible which can access old state
> + * so it is worth keeping them all.
> + */
> for (i = 0; i < KVM_NR_SPSR; i++) {
> reg.id = AARCH64_CORE_REG(spsr[i]);
> - reg.addr = (uintptr_t) &env->banked_spsr[i - 1];
> + reg.addr = (uintptr_t) &env->banked_spsr[i+1];
> ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
> if (ret) {
> return ret;
> }
> }
>
> + el = arm_current_el(env);
> + if (is_a64(env) && el > 0) {
> + g_assert(el == 1);
> + /* KVM maps KVM_SPSR_SVC to KVM_SPSR_EL1 for aarch64 */
> + env->banked_spsr[0] = env->banked_spsr[1];
> + env->spsr = env->banked_spsr[aarch64_banked_spsr_index(el)];
> + } else {
> + env->spsr = env->banked_spsr[el];
same concern with bank_number as above.
> + }
> +
> /* Advanced SIMD and FP registers */
> for (i = 0; i < 32; i++) {
> reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
> --
> 2.3.0
>
Thanks,
-Christoffer
next prev parent reply other threads:[~2015-03-02 17:23 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-02-25 16:02 [Qemu-devel] [PATCH 0/6] QEMU ARM64 Migration Fixes Alex Bennée
2015-02-25 16:02 ` [Qemu-devel] [PATCH 1/6] target-arm: kvm: save/restore mp state Alex Bennée
2015-02-25 23:36 ` Peter Maydell
2015-03-03 10:56 ` Alex Bennée
2015-03-03 11:06 ` Paolo Bonzini
2015-03-03 11:51 ` Peter Maydell
2015-03-03 16:30 ` Alex Bennée
2015-03-03 17:10 ` Paolo Bonzini
2015-02-26 12:57 ` Paolo Bonzini
2015-02-25 16:02 ` [Qemu-devel] [PATCH 2/6] arm_gic_kvm.c: restore config before pending IRQs Alex Bennée
2015-03-02 22:14 ` Christoffer Dall
2015-02-25 16:02 ` [Qemu-devel] [PATCH 3/6] hw/char/pl011: don't keep setting the IRQ if nothing changed Alex Bennée
2015-02-25 16:02 ` [Qemu-devel] [PATCH 4/6] target-arm/kvm64.c: sync FP register state Alex Bennée
2015-02-25 16:02 ` [Qemu-devel] [PATCH 5/6] target-arm/kvm64: fix save/restore of SPSR registers Alex Bennée
2015-02-25 16:02 ` [Qemu-devel] [PATCH 5/6] target-arm/kvm64: fix save/restore of SPSR regs Alex Bennée
2015-03-02 17:22 ` Christoffer Dall [this message]
2015-03-03 11:28 ` Alex Bennée
2015-03-09 12:56 ` Christoffer Dall
2015-03-09 13:31 ` Peter Maydell
2015-03-09 16:25 ` Alex Bennée
2015-03-09 19:31 ` Christoffer Dall
2015-02-25 16:02 ` [Qemu-devel] [PATCH 6/6] target-arm/cpu.h: document why env->spsr exists Alex Bennée
2015-03-11 15:39 ` Greg Bellows
2015-03-11 15:47 ` Peter Maydell
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