From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33401) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YVMuX-0008Q2-1V for qemu-devel@nongnu.org; Tue, 10 Mar 2015 12:21:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YVMuT-0003wL-Iy for qemu-devel@nongnu.org; Tue, 10 Mar 2015 12:21:36 -0400 Date: Tue, 10 Mar 2015 17:21:06 +0100 From: "Michael S. Tsirkin" Message-ID: <20150310172000-mutt-send-email-mst@redhat.com> References: <1426001534-7151-1-git-send-email-marcel@redhat.com> <1426001534-7151-28-git-send-email-marcel@redhat.com> <20150310164158-mutt-send-email-mst@redhat.com> <54FF199F.5010002@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <54FF199F.5010002@redhat.com> Subject: Re: [Qemu-devel] [PATCH v5 for-2.3 27/28] apci: fix PXB behaviour if used with unsupported BIOS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: kraxel@redhat.com, quintela@redhat.com, seabios@seabios.org, qemu-devel@nongnu.org, agraf@suse.de, alex.williamson@redhat.com, kevin@koconnor.net, qemu-ppc@nongnu.org, hare@suse.de, imammedo@redhat.com, amit.shah@redhat.com, pbonzini@redhat.com, leon.alrae@imgtec.com, aurelien@aurel32.net, rth@twiddle.net On Tue, Mar 10, 2015 at 06:19:43PM +0200, Marcel Apfelbaum wrote: > On 03/10/2015 05:44 PM, Michael S. Tsirkin wrote: > >On Tue, Mar 10, 2015 at 05:32:13PM +0200, Marcel Apfelbaum wrote: > >>PXB does not work with an unsupported BIOS, but should > >>not interfere with normal OS operation. > >> > >>Fix this by not adding PXB mem/IO chunks to _CRS > >>if they weren't configured by BIOS. > >> > >>Signed-off-by: Marcel Apfelbaum > >>--- > >> hw/i386/acpi-build.c | 71 +++++++++++++++++++++++++++++++--------------------- > >> 1 file changed, 42 insertions(+), 29 deletions(-) > >> > >>diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > >>index 2bc8a80..416972c 100644 > >>--- a/hw/i386/acpi-build.c > >>+++ b/hw/i386/acpi-build.c > >>@@ -780,6 +780,10 @@ static Aml *build_crs(PcPciInfo *pci, PciInfo *bus_info, > >> range_base = region->value->address; > >> range_limit = region->value->address + region->value->size - 1; > >> > >>+ if (range_base == PCI_BAR_UNMAPPED) { > >>+ continue; > >>+ } > >>+ > >> if (!strcmp(region->value->type, "io")) { > >> aml_append(crs, > >> aml_word_io(aml_min_fixed, aml_max_fixed, > >>@@ -813,41 +817,50 @@ static Aml *build_crs(PcPciInfo *pci, PciInfo *bus_info, > >> > >> range_base = bridge_info->bus.io_range->base; > >> range_limit = bridge_info->bus.io_range->limit; > >>- aml_append(crs, > >>- aml_word_io(aml_min_fixed, aml_max_fixed, > >>- aml_pos_decode, aml_entire_range, > >>- 0, > >>- range_base, > >>- range_limit, > >>- 0, > >>- range_limit - range_base + 1)); > >>- crs_range_insert(io_ranges, range_base, range_limit); > >>+ /* PCI Bridge I/O limit is aligned to 4K */ > > > >Can't say this comment explains anything. > >So it's aligned - thus if (range_limit >> 12) is same as > >if (range_limit). > I'll use range_base == 0 as invalid value. > > Thanks, > Marcel It's also just a work-around for old broken bioses. We don't ship them anymore, but it's reasonable to keep around until we update the bios in qemu. However, pls add a comment to this end. > > > >Also, generally you should test limit>base for bridges. > > > > >>+ if (range_limit >> 12) { > >>+ aml_append(crs, > >>+ aml_word_io(aml_min_fixed, aml_max_fixed, > >>+ aml_pos_decode, aml_entire_range, > >>+ 0, > >>+ range_base, > >>+ range_limit, > >>+ 0, > >>+ range_limit - range_base + 1)); > >>+ crs_range_insert(io_ranges, range_base, range_limit); > >>+ } > >> > >> range_base = bridge_info->bus.memory_range->base; > >> range_limit = bridge_info->bus.memory_range->limit; > >>- aml_append(crs, > >>- aml_dword_memory(aml_pos_decode, aml_min_fixed, > >>- aml_max_fixed, aml_non_cacheable, > >>- aml_ReadWrite, > >>- 0, > >>- range_base, > >>- range_limit, > >>- 0, > >>- range_limit - range_base + 1)); > >>- crs_range_insert(mem_ranges, range_base, range_limit); > >>+ /* PCI Bridge MEM limit is aligned to 1M */ > > > >same comment here. > > > >>+ if (range_limit >> 20) { > >>+ aml_append(crs, > >>+ aml_dword_memory(aml_pos_decode, aml_min_fixed, > >>+ aml_max_fixed, aml_non_cacheable, > >>+ aml_ReadWrite, > >>+ 0, > >>+ range_base, > >>+ range_limit, > >>+ 0, > >>+ range_limit - range_base + 1)); > >>+ crs_range_insert(mem_ranges, range_base, range_limit); > >>+ } > >> > >> range_base = bridge_info->bus.prefetchable_range->base; > >> range_limit = bridge_info->bus.prefetchable_range->limit; > >>- aml_append(crs, > >>- aml_dword_memory(aml_pos_decode, aml_min_fixed, > >>- aml_max_fixed, aml_non_cacheable, > >>- aml_ReadWrite, > >>- 0, > >>- range_base, > >>- range_limit, > >>- 0, > >>- range_limit - range_base + 1)); > >>- crs_range_insert(mem_ranges, range_base, range_limit); > >>+ /* PCI Bridge Prefetch MEM limit is aligned to 1M */ > >>+ if (range_limit >> 20) { > >>+ aml_append(crs, > >>+ aml_dword_memory(aml_pos_decode, aml_min_fixed, > >>+ aml_max_fixed, aml_non_cacheable, > >>+ aml_ReadWrite, > >>+ 0, > >>+ range_base, > >>+ range_limit, > >>+ 0, > >>+ range_limit - range_base + 1)); > >>+ crs_range_insert(mem_ranges, range_base, range_limit); > >>+ } > >> } > >> } > >> > >>-- > >>2.1.0