qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Daniel P. Berrange" <berrange@redhat.com>
To: Eduardo Habkost <ehabkost@redhat.com>
Cc: libvir-list@redhat.com, qemu-devel@nongnu.org,
	donald.d.dugger@intel.com, jun.nakajima@intel.com,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Jiri Denemark" <jdenemar@redhat.com>,
	"Andreas Färber" <afaerber@suse.de>
Subject: Re: [Qemu-devel] [PATCH 2/2] target-i386: Haswell-noTSX and Broadwell-noTSX
Date: Mon, 16 Mar 2015 10:24:51 +0000	[thread overview]
Message-ID: <20150316102451.GD10189@redhat.com> (raw)
In-Reply-To: <1426273797-11204-3-git-send-email-ehabkost@redhat.com>

On Fri, Mar 13, 2015 at 04:09:57PM -0300, Eduardo Habkost wrote:
> With the Intel microcode update that removed HLE and RTM, there will be
> different kinds of Haswell and Broadwell CPUs out there: some that still
> have the HLE and RTM features, and some that don't have the HLE and RTM
> features. On both cases people may be willing to use the pc-*-2.3
> machine-types.
> 
> So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU
> models, for hosts that have Haswell and Broadwell CPUs without TSX support.
> 
> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>

The addition of Haswell-noTSX looks good to me.

I'm unclear on whether we truely need Broadwell-noTSX though. Did
Intel actually ship any Broadwell production silicon in which the
microcode disables this feature, or was it only a problem on
pre-production samples of Broadwell ? If the latter, I'd say we
don't need to have a Broadwell-noTSX model added. Perhaps Jun/Don
can confirm from Intel's side.


> ---
>  target-i386/cpu.c | 69 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index de3cdce..b693bab 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -1073,6 +1073,39 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
>      },
>      {
> +        .name = "Haswell-noTSX",
> +        .level = 0xd,
> +        .vendor = CPUID_VENDOR_INTEL,
> +        .family = 6,
> +        .model = 60,
> +        .stepping = 1,
> +        .features[FEAT_1_EDX] =
> +            CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> +            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
> +            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> +            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> +            CPUID_DE | CPUID_FP87,
> +        .features[FEAT_1_ECX] =
> +            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
> +            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
> +            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> +            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
> +            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
> +            CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
> +        .features[FEAT_8000_0001_EDX] =
> +            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
> +            CPUID_EXT2_SYSCALL,
> +        .features[FEAT_8000_0001_ECX] =
> +            CPUID_EXT3_LAHF_LM,
> +        .features[FEAT_7_0_EBX] =
> +            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> +            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> +            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
> +        .features[FEAT_XSAVE] =
> +            CPUID_XSAVE_XSAVEOPT,
> +        .xlevel = 0x8000000A,
> +        .model_id = "Intel Core Processor (Haswell, no TSX)",
> +    },    {
>          .name = "Haswell",
>          .level = 0xd,
>          .vendor = CPUID_VENDOR_INTEL,
> @@ -1108,6 +1141,42 @@ static X86CPUDefinition builtin_x86_defs[] = {
>          .model_id = "Intel Core Processor (Haswell)",
>      },
>      {
> +        .name = "Broadwell-noTSX",
> +        .level = 0xd,
> +        .vendor = CPUID_VENDOR_INTEL,
> +        .family = 6,
> +        .model = 61,
> +        .stepping = 2,
> +        .features[FEAT_1_EDX] =
> +            CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
> +            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
> +            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
> +            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
> +            CPUID_DE | CPUID_FP87,
> +        .features[FEAT_1_ECX] =
> +            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
> +            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
> +            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
> +            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
> +            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
> +            CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
> +        .features[FEAT_8000_0001_EDX] =
> +            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
> +            CPUID_EXT2_SYSCALL,
> +        .features[FEAT_8000_0001_ECX] =
> +            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
> +        .features[FEAT_7_0_EBX] =
> +            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> +            CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
> +            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
> +            CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
> +            CPUID_7_0_EBX_SMAP,
> +        .features[FEAT_XSAVE] =
> +            CPUID_XSAVE_XSAVEOPT,
> +        .xlevel = 0x8000000A,
> +        .model_id = "Intel Core Processor (Broadwell, no TSX)",
> +    },
> +    {
>          .name = "Broadwell",
>          .level = 0xd,
>          .vendor = CPUID_VENDOR_INTEL,

Regards,
Daniel
-- 
|: http://berrange.com      -o-    http://www.flickr.com/photos/dberrange/ :|
|: http://libvirt.org              -o-             http://virt-manager.org :|
|: http://autobuild.org       -o-         http://search.cpan.org/~danberr/ :|
|: http://entangle-photo.org       -o-       http://live.gnome.org/gtk-vnc :|

  reply	other threads:[~2015-03-16 10:25 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-13 19:09 [Qemu-devel] [PATCH 0/2] target-i386: Haswell-noTSX and Broadwell-noTSX CPU models Eduardo Habkost
2015-03-13 19:09 ` [Qemu-devel] [PATCH 1/2] Revert "target-i386: Disable HLE and RTM on Haswell & Broadwell" Eduardo Habkost
2015-03-16 10:18   ` Daniel P. Berrange
2015-03-13 19:09 ` [Qemu-devel] [PATCH 2/2] target-i386: Haswell-noTSX and Broadwell-noTSX Eduardo Habkost
2015-03-16 10:24   ` Daniel P. Berrange [this message]
2015-03-19 18:02     ` Eduardo Habkost
2015-03-19 18:14       ` Daniel P. Berrange
2015-03-13 19:25 ` [Qemu-devel] [PATCH 0/2] target-i386: Haswell-noTSX and Broadwell-noTSX CPU models Andreas Färber
2015-03-13 19:45   ` Eduardo Habkost
2015-03-14 11:42     ` Andreas Färber

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20150316102451.GD10189@redhat.com \
    --to=berrange@redhat.com \
    --cc=afaerber@suse.de \
    --cc=donald.d.dugger@intel.com \
    --cc=ehabkost@redhat.com \
    --cc=jdenemar@redhat.com \
    --cc=jun.nakajima@intel.com \
    --cc=libvir-list@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).