From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32925) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXx3u-0004GQ-Or for qemu-devel@nongnu.org; Tue, 17 Mar 2015 15:21:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YXx3q-0007A9-KL for qemu-devel@nongnu.org; Tue, 17 Mar 2015 15:21:58 -0400 Received: from mail-la0-f51.google.com ([209.85.215.51]:34693) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YXx3q-00079u-Di for qemu-devel@nongnu.org; Tue, 17 Mar 2015 15:21:54 -0400 Received: by lagg8 with SMTP id g8so17597701lag.1 for ; Tue, 17 Mar 2015 12:21:53 -0700 (PDT) Date: Tue, 17 Mar 2015 20:22:20 +0100 From: Christoffer Dall Message-ID: <20150317192220.GA23225@cbox> References: <1426619975-2346-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1426619975-2346-1-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: kvmarm@lists.cs.columbia.edu, Greg Bellows , Alex =?iso-8859-1?Q?Benn=E9e?= , qemu-devel@nongnu.org, patches@linaro.org On Tue, Mar 17, 2015 at 07:19:35PM +0000, Peter Maydell wrote: > The AArch64 SPSR_EL1 register is architecturally mandated to > be mapped to the AArch32 SPSR_svc register. This means its > state should live in QEMU's env->banked_spsr[1] field. > Correct the buggy regdef that put it in banked_spsr[0] instead. > > Signed-off-by: Peter Maydell > --- > target-arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 10886c5..d77c6de 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64, > .type = ARM_CP_ALIAS, > .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0, > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) }, > + .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) }, > /* We rely on the access checks not allowing the guest to write to the > * state field when SPSel indicates that it's being used as the stack > * pointer. > -- > 1.9.1 > Don't you need to change aarch64_banked_spsr_index() accordingly? -Christoffer