From: Christoffer Dall <christoffer.dall@linaro.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: kvmarm@lists.cs.columbia.edu,
"Greg Bellows" <greg.bellows@linaro.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH v2] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
Date: Tue, 17 Mar 2015 20:38:16 +0100 [thread overview]
Message-ID: <20150317193816.GB23225@cbox> (raw)
In-Reply-To: <1426620735-2454-1-git-send-email-peter.maydell@linaro.org>
On Tue, Mar 17, 2015 at 07:32:15PM +0000, Peter Maydell wrote:
> The AArch64 SPSR_EL1 register is architecturally mandated to
> be mapped to the AArch32 SPSR_svc register. This means its
> state should live in QEMU's env->banked_spsr[1] field.
> Correct the various places in the code that incorrectly
> put it in banked_spsr[0].
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Alex, will you respin the SPSR patch based on this one then? You can
change the authorship on the SPSR patch to yourself if you prefer.
Thanks,
-Christoffer
next prev parent reply other threads:[~2015-03-17 19:37 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-17 19:32 [Qemu-devel] [PATCH v2] target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc) Peter Maydell
2015-03-17 19:38 ` Christoffer Dall [this message]
2015-03-17 19:44 ` Peter Maydell
2015-03-18 13:58 ` Alex Bennée
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