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From: "Michael S. Tsirkin" <mst@redhat.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: xen-devel@lists.xensource.com, pmatouse@redhat.com,
	qemu-devel@nongnu.org,
	Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Subject: Re: [Qemu-devel] [Xen-devel] [PATCH][XSA-126] xen: limit guest control of PCI command register
Date: Wed, 1 Apr 2015 11:59:40 +0200	[thread overview]
Message-ID: <20150401115032-mutt-send-email-mst@redhat.com> (raw)
In-Reply-To: <551BBD38.60204@citrix.com>

On Wed, Apr 01, 2015 at 10:41:12AM +0100, Andrew Cooper wrote:
> On 01/04/15 10:20, Stefano Stabellini wrote:
> > CC'ing the author of the patch and xen-devel.
> > FYI I think that Jan is going to be on vacation for a couple of weeks.
> >
> > On Wed, 1 Apr 2015, Michael S. Tsirkin wrote:
> >> On Tue, Mar 31, 2015 at 03:18:03PM +0100, Stefano Stabellini wrote:
> >>> From: Jan Beulich <jbeulich@suse.com>
> >>>
> >>> Otherwise the guest can abuse that control to cause e.g. PCIe
> >>> Unsupported Request responses (by disabling memory and/or I/O decoding
> >>> and subsequently causing [CPU side] accesses to the respective address
> >>> ranges), which (depending on system configuration) may be fatal to the
> >>> host.
> >>>
> >>> This is CVE-2015-2756 / XSA-126.
> >>>
> >>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
> >>> Reviewed-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
> >>> Acked-by: Ian Campbell <ian.campbell@citrix.com>
> >> The patch description seems somewhat incorrect to me.
> >> UR should not be fatal to the system, and it's not platform
> >> specific.
> > I think that people have been able to repro this, but I'll let Jan
> > comment on it.
> 
> Depending on how the BIOS sets up AER (if even available), a UR can very
> easily be fatal to the system.
> 
> If firmware first mode is set, Xen (or indeed Linux) can't fix a
> problematic setup.  Experimentally, doing so can cause infinite loops in
> certain vendors SMM handlers.

I think it can, just disable UR reporting, this is up to OS.  This is
what the PCI spec says - you have snipped the relevant part out from the
mail you are replying to.

> >
> >> In particular, there could be more reasons for devices
> >> to generate URs, for example, if they get a transaction
> >> during FLR. I don't think we ever tried to prevent this.
> > That cannot be triggered by guest behaviour.
> 
> What cannot be triggered by guest behaviour?
> 
> Many devices have secondary access into config space via a BAR, which
> allows a guest driver full and unmediated control of everything.
> 
> Under Xen, we have covered this with XSA-124 which basically says that
> for such devices, all bets are off.
> 
> ~Andrew

That one basically says don't pass through PFs if you want security :)
One has to wonder what's the point of XA-126 is then, it can only be
triggered with PFs.
I guess it'd apply to the theorectically possible "devices the entire
scope of whose functionality is known and has been reviewed for PCI
passthrough security and correctness". Do you know of such hardware
in real life?

-- 
MST

  reply	other threads:[~2015-04-01  9:59 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-03-31 14:18 [Qemu-devel] [PATCH][XSA-126] xen: limit guest control of PCI command register Stefano Stabellini
2015-04-01  9:01 ` Michael S. Tsirkin
2015-04-01  9:20   ` Stefano Stabellini
2015-04-01  9:32     ` Michael S. Tsirkin
2015-04-01  9:41     ` [Qemu-devel] [Xen-devel] " Andrew Cooper
2015-04-01  9:59       ` Michael S. Tsirkin [this message]
2015-04-13  8:17         ` Jan Beulich
2015-04-13 11:19           ` Michael S. Tsirkin
2015-04-13 11:34             ` Jan Beulich
2015-04-13 11:47               ` Michael S. Tsirkin
2015-04-13 12:40                 ` Jan Beulich
2015-04-13 12:47                   ` Michael S. Tsirkin
2015-04-13 12:51                     ` Jan Beulich
2015-04-20 13:43                       ` Michael S. Tsirkin
2015-04-20 14:08                         ` Jan Beulich
2015-04-20 14:32                           ` Michael S. Tsirkin
2015-04-20 14:57                             ` Jan Beulich
2015-06-07  6:23                             ` Michael S. Tsirkin
2015-06-08  7:42                               ` Jan Beulich
2015-06-08  8:09                                 ` Malcolm Crossley
2015-06-08  8:59                                   ` Michael S. Tsirkin
2015-06-08  9:03                                   ` Jan Beulich
2015-06-08  9:36                                     ` Michael S. Tsirkin
2015-06-08 10:55                                       ` Jan Beulich
2015-06-08 11:28                                         ` Michael S. Tsirkin
2015-06-08 11:44                                           ` Jan Beulich
2015-06-10  7:00                                           ` Jan Beulich
2015-06-10 11:43                                             ` Michael S. Tsirkin
2015-06-10 12:06                                               ` Jan Beulich
2015-06-10 13:35                                                 ` Michael S. Tsirkin
2015-06-08  9:30                                 ` Michael S. Tsirkin
2015-06-08 10:38                                   ` Jan Beulich
2015-06-10  7:08                                   ` Jan Beulich
2015-06-10 11:46                                     ` Michael S. Tsirkin
2015-06-10 12:10                                       ` Jan Beulich
2015-04-01  9:50     ` Ian Campbell
2015-04-01 10:12       ` Michael S. Tsirkin
2015-04-09 18:10 ` [Qemu-devel] " Peter Maydell
2015-04-10 11:45   ` Peter Maydell
2015-04-10 11:49     ` Peter Maydell

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