From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32794) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YfPsJ-00013r-5f for qemu-devel@nongnu.org; Tue, 07 Apr 2015 05:32:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YfPsF-0004n1-3y for qemu-devel@nongnu.org; Tue, 07 Apr 2015 05:32:51 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60015) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YfPsE-0004me-S8 for qemu-devel@nongnu.org; Tue, 07 Apr 2015 05:32:47 -0400 Date: Tue, 7 Apr 2015 11:32:39 +0200 From: "Michael S. Tsirkin" Message-ID: <20150407113100-mutt-send-email-mst@redhat.com> References: <1428055432-12120-1-git-send-email-zhaoshenglong@huawei.com> <1428346052.2973.26.camel@deneb.redhat.com> <55234469.9060404@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v4 00/20] Generate ACPI v5.1 tables and expose it to guest over fw_cfg on ARM List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: hangaohuai@huawei.com, Igor Mammedov , Alexander Spyridakis , Shannon Zhao , Claudio Fontana , QEMU Developers , "Huangpeng (Peter)" , Hanjun Guo , Mark Salter , Paolo Bonzini , Laszlo Ersek , Christoffer Dall , Shannon Zhao On Tue, Apr 07, 2015 at 10:19:22AM +0100, Peter Maydell wrote: > On 7 April 2015 at 03:43, Shannon Zhao wrote: > > The dts node is: > > ranges = <0x1000000 0x0 0x0 0x0 0x3eff0000 0x0 0x10000 > > 0x2000000 0x0 0x10000000 0x0 0x10000000 0x0 0x2eff0000>; > > reg = <0x0 0x3f000000 0x0 0x1000000>; > > bus-range = <0x0 0xf>; > > > > The ACPI table entry: > > Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address > > { > > Return (0x3F000000) > > } > > Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings > > { > > Name (RBUF, ResourceTemplate () > > { > > WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, > > 0x0000, // Granularity > > 0x0000, // Range Minimum > > 0x000F, // Range Maximum > > 0x0000, // Translation Offset > > 0x0010, // Length > > ,, ) > > DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, > > Is this claiming that the non-cacheable PCI MMIO region is cacheable? > If so that isn't right... I suspect that's fine. Some parts of MMIO might be cacheable. This really depends on the device. > > 0x00000000, // Granularity > > 0x10000000, // Range Minimum > > 0x3EFF0000, // Range Maximum > > 0x00000000, // Translation Offset > > 0x2EFF0000, // Length > > ,, , AddressRangeMemory, TypeStatic) > > DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, > > 0x00000000, // Granularity > > 0x3EFF0000, // Range Minimum > > 0x3F000000, // Range Maximum > > 0x00000000, // Translation Offset > > I rather suspect this is wrong, since (my guess without looking > at the spec) it looks like it defines a 1:1 mapping between > the addresses used to interact with the PCIe IO window and > the IO addresses, which is obviously not what you want. > My guess is you need to set the translation offset at least, > but check the spec. > > -- PMM