From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47967) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YkMQ3-0006aU-0o for qemu-devel@nongnu.org; Mon, 20 Apr 2015 20:52:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YkMPy-0000JP-5j for qemu-devel@nongnu.org; Mon, 20 Apr 2015 20:52:06 -0400 Received: from mail-yh0-x235.google.com ([2607:f8b0:4002:c01::235]:36566) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YkMPy-0000JD-0J for qemu-devel@nongnu.org; Mon, 20 Apr 2015 20:52:02 -0400 Received: by yhrr66 with SMTP id r66so7059005yhr.3 for ; Mon, 20 Apr 2015 17:52:00 -0700 (PDT) Date: Tue, 21 Apr 2015 10:49:11 +1000 From: "Edgar E. Iglesias" Message-ID: <20150421004911.GA11707@toto> References: <1429113742-8371-1-git-send-email-greg.bellows@linaro.org> <1429113742-8371-6-git-send-email-greg.bellows@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1429113742-8371-6-git-send-email-greg.bellows@linaro.org> Subject: Re: [Qemu-devel] [PATCH v3 05/16] hw/intc/arm_gic: Add ns_access() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, Fabian Aggeler On Wed, Apr 15, 2015 at 11:02:11AM -0500, Greg Bellows wrote: > From: Fabian Aggeler > > Security Extensions for GICv1 and GICv2 use register banking > to provide transparent access to seperate Secure and Non-secure > copies of GIC configuration registers. This function will later > be replaced by code determining the security state of a read/write > access to a register. Hi, Can we rebase this on top of Peters memory attribute series to get the actual secure attribute? Cheers, Edgar > > Signed-off-by: Fabian Aggeler > Signed-off-by: Greg Bellows > --- > hw/intc/arm_gic.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index cdf7408..e0bce6e 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -45,6 +45,13 @@ static inline int gic_get_current_cpu(GICState *s) > return 0; > } > > +/* Security state of a read / write access */ > +static inline bool ns_access(void) > +{ > + /* TODO: use actual security state */ > + return true; > +} > + > /* TODO: Many places that call this routine could be optimized. */ > /* Update interrupt status after enabled or pending bits have been changed. */ > void gic_update(GICState *s) > -- > 1.8.3.2 > >