From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54888) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpRMm-0006OI-FV for qemu-devel@nongnu.org; Mon, 04 May 2015 21:09:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YpRMj-0003ol-6o for qemu-devel@nongnu.org; Mon, 04 May 2015 21:09:44 -0400 Received: from mail-wg0-x22a.google.com ([2a00:1450:400c:c00::22a]:34889) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpRMi-0003oa-Sr for qemu-devel@nongnu.org; Mon, 04 May 2015 21:09:41 -0400 Received: by wgyo15 with SMTP id o15so166853890wgy.2 for ; Mon, 04 May 2015 18:09:40 -0700 (PDT) Date: Tue, 5 May 2015 11:06:14 +1000 From: "Edgar E. Iglesias" Message-ID: <20150505010614.GI10142@toto> References: <1430502643-25909-1-git-send-email-peter.maydell@linaro.org> <1430502643-25909-8-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1430502643-25909-8-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH v4 07/17] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Greg Bellows , qemu-devel@nongnu.org, patches@linaro.org On Fri, May 01, 2015 at 06:50:33PM +0100, Peter Maydell wrote: > From: Fabian Aggeler > > This register is banked in GICs with Security Extensions. Storing the > non-secure copy of BPR in the abpr, which is an alias to the non-secure > copy for secure access. ABPR itself is only accessible from secure state > if the GIC implements Security Extensions. > > Signed-off-by: Fabian Aggeler > Signed-off-by: Greg Bellows > Message-id: 1429113742-8371-10-git-send-email-greg.bellows@linaro.org > [PMM: rewrote to fix style issues and correct handling of GICv2 > without security extensions] > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > hw/intc/arm_gic.c | 31 ++++++++++++++++++++++++++----- > include/hw/intc/arm_gic_common.h | 11 ++++++++--- > 2 files changed, 34 insertions(+), 8 deletions(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 4f13ff2..e6ad8de 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -762,7 +762,12 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, > *data = s->priority_mask[cpu]; > break; > case 0x08: /* Binary Point */ > - *data = s->bpr[cpu]; > + if (s->security_extn && !attrs.secure) { > + /* BPR is banked. Non-secure copy stored in ABPR. */ > + *data = s->abpr[cpu]; > + } else { > + *data = s->bpr[cpu]; > + } > break; > case 0x0c: /* Acknowledge */ > *data = gic_acknowledge_irq(s, cpu); > @@ -774,7 +779,16 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, > *data = s->current_pending[cpu]; > break; > case 0x1c: /* Aliased Binary Point */ > - *data = s->abpr[cpu]; > + /* GIC v2, no security: ABPR > + * GIC v1, no security: not implemented (RAZ/WI) > + * With security extensions, secure access: ABPR (alias of NS BPR) > + * With security extensions, nonsecure access: RAZ/WI > + */ > + if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { > + *data = 0; > + } else { > + *data = s->abpr[cpu]; > + } > break; > case 0xd0: case 0xd4: case 0xd8: case 0xdc: > *data = s->apr[(offset - 0xd0) / 4][cpu]; > @@ -799,14 +813,21 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, > s->priority_mask[cpu] = (value & 0xff); > break; > case 0x08: /* Binary Point */ > - s->bpr[cpu] = (value & 0x7); > + if (s->security_extn && !attrs.secure) { > + s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); > + } else { > + s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); > + } > break; > case 0x10: /* End Of Interrupt */ > gic_complete_irq(s, cpu, value & 0x3ff); > return MEMTX_OK; > case 0x1c: /* Aliased Binary Point */ > - if (s->revision >= 2) { > - s->abpr[cpu] = (value & 0x7); > + if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) { > + /* unimplemented, or NS access: RAZ/WI */ > + return MEMTX_OK; > + } else { > + s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); > } > break; > case 0xd0: case 0xd4: case 0xd8: case 0xdc: > diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h > index d5d3877..261402f 100644 > --- a/include/hw/intc/arm_gic_common.h > +++ b/include/hw/intc/arm_gic_common.h > @@ -34,6 +34,9 @@ > #define MAX_NR_GROUP_PRIO 128 > #define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32) > > +#define GIC_MIN_BPR 0 > +#define GIC_MIN_ABPR (GIC_MIN_BPR + 1) > + > typedef struct gic_irq_state { > /* The enable bits are only banked for per-cpu interrupts. */ > uint8_t enabled; > @@ -76,9 +79,11 @@ typedef struct GICState { > uint16_t running_priority[GIC_NCPU]; > uint16_t current_pending[GIC_NCPU]; > > - /* We present the GICv2 without security extensions to a guest and > - * therefore the guest can configure the GICC_CTLR to configure group 1 > - * binary point in the abpr. > + /* If we present the GICv2 without security extensions to a guest, > + * the guest can configure the GICC_CTLR to configure group 1 binary point > + * in the abpr. > + * For a GIC with Security Extensions we use use bpr for the > + * secure copy and abpr as storage for the non-secure copy of the register. > */ > uint8_t bpr[GIC_NCPU]; > uint8_t abpr[GIC_NCPU]; > -- > 1.9.1 >