From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38645) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpRxE-0006H1-Pi for qemu-devel@nongnu.org; Mon, 04 May 2015 21:47:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YpRxB-0006zv-JS for qemu-devel@nongnu.org; Mon, 04 May 2015 21:47:24 -0400 Received: from mail-pa0-x22d.google.com ([2607:f8b0:400e:c03::22d]:35846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpRxB-0006za-Bx for qemu-devel@nongnu.org; Mon, 04 May 2015 21:47:21 -0400 Received: by pabsx10 with SMTP id sx10so176695009pab.3 for ; Mon, 04 May 2015 18:47:18 -0700 (PDT) Date: Tue, 5 May 2015 11:43:52 +1000 From: "Edgar E. Iglesias" Message-ID: <20150505014352.GM10142@toto> References: <1430502643-25909-1-git-send-email-peter.maydell@linaro.org> <1430502643-25909-12-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1430502643-25909-12-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH v4 11/17] hw/intc/arm_gic: Handle grouping for GICC_HPPIR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Greg Bellows , qemu-devel@nongnu.org, patches@linaro.org On Fri, May 01, 2015 at 06:50:37PM +0100, Peter Maydell wrote: > From: Fabian Aggeler > > Grouping (GICv2) and Security Extensions change the behaviour of reads > of the highest priority pending interrupt register (ICCHPIR/GICC_HPPIR). > > Signed-off-by: Fabian Aggeler > Signed-off-by: Greg Bellows > Message-id: 1429113742-8371-12-git-send-email-greg.bellows@linaro.org > [PMM: make utility fn static; coding style fixes; AckCtl has an effect > for GICv2 without security extensions as well; removed checks on enable > bits because these are done when we set current_pending[cpu]] > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > hw/intc/arm_gic.c | 28 +++++++++++++++++++++++++++- > 1 file changed, 27 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c > index 7c0ddc8..75c69b3 100644 > --- a/hw/intc/arm_gic.c > +++ b/hw/intc/arm_gic.c > @@ -176,6 +176,32 @@ static void gic_set_irq(void *opaque, int irq, int level) > gic_update(s); > } > > +static uint16_t gic_get_current_pending_irq(GICState *s, int cpu, > + MemTxAttrs attrs) > +{ > + uint16_t pending_irq = s->current_pending[cpu]; > + > + if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) { > + int group = GIC_TEST_GROUP(pending_irq, (1 << cpu)); > + /* On a GIC without the security extensions, reading this register > + * behaves in the same way as a secure access to a GIC with them. > + */ > + bool secure = !s->security_extn || attrs.secure; > + > + if (group == 0 && !secure) { > + /* Group0 interrupts hidden from Non-secure access */ > + return 1023; > + } > + if (group == 1 && secure && !(s->cpu_ctlr[cpu] & GICC_CTLR_ACK_CTL)) { > + /* Group1 interrupts only seen by Secure access if > + * AckCtl bit set. > + */ > + return 1022; > + } > + } > + return pending_irq; > +} > + > static void gic_set_running_irq(GICState *s, int cpu, int irq) > { > s->running_irq[cpu] = irq; > @@ -890,7 +916,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, > *data = gic_get_running_priority(s, cpu, attrs); > break; > case 0x18: /* Highest Pending Interrupt */ > - *data = s->current_pending[cpu]; > + *data = gic_get_current_pending_irq(s, cpu, attrs); > break; > case 0x1c: /* Aliased Binary Point */ > /* GIC v2, no security: ABPR > -- > 1.9.1 >