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Date: Wed, 6 May 2015 09:58:09 +0530
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
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Subject: Re: [Qemu-devel] [RFC PATCH v3 06/24] spapr: Consolidate cpu init
 code into a routine
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To: Thomas Huth <thuth@redhat.com>
Cc: mdroth@linux.vnet.ibm.com, aik@ozlabs.ru, agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, tyreld@linux.vnet.ibm.com, imammedo@redhat.com, nfont@linux.vnet.ibm.com, afaerber@suse.de, david@gibson.dropbear.id.au

On Mon, May 04, 2015 at 06:10:59PM +0200, Thomas Huth wrote:
> On Fri, 24 Apr 2015 12:17:28 +0530
> Bharata B Rao <bharata@linux.vnet.ibm.com> wrote:
> 
> > Factor out bits of sPAPR specific CPU initialization code into
> > a separate routine so that it can be called from CPU hotplug
> > path too.
> > 
> > Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
> > Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> >  hw/ppc/spapr.c | 54 +++++++++++++++++++++++++++++-------------------------
> >  1 file changed, 29 insertions(+), 25 deletions(-)
> > 
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index a56f9a1..5c8f2ff 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -1440,6 +1440,34 @@ static void spapr_drc_reset(void *opaque)
> >      }
> >  }
> >  
> > +static void spapr_cpu_init(PowerPCCPU *cpu)
> > +{
> > +    CPUPPCState *env = &cpu->env;
> > +
> > +    /* Set time-base frequency to 512 MHz */
> > +    cpu_ppc_tb_init(env, TIMEBASE_FREQ);
> > +
> > +    /* PAPR always has exception vectors in RAM not ROM. To ensure this,
> > +     * MSR[IP] should never be set.
> > +     */
> > +    env->msr_mask &= ~(1 << 6);
> 
> While you're at it ... could we maybe get a proper #define for that MSR
> bit? (just like the other ones in target-ppc/cpu.h)

Sure will use MSR_EP here next time.

Regards,
Bharata.