From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36565) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ypuyc-0006WR-KD for qemu-devel@nongnu.org; Wed, 06 May 2015 04:46:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YpuyX-000896-Kj for qemu-devel@nongnu.org; Wed, 06 May 2015 04:46:46 -0400 Received: from e23smtp08.au.ibm.com ([202.81.31.141]:59454) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YpuyW-00088R-WC for qemu-devel@nongnu.org; Wed, 06 May 2015 04:46:41 -0400 Received: from /spool/local by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 6 May 2015 18:46:36 +1000 Date: Wed, 6 May 2015 14:15:37 +0530 From: Bharata B Rao Message-ID: <20150506084537.GV18380@in.ibm.com> References: <1429858066-12088-1-git-send-email-bharata@linux.vnet.ibm.com> <1429858066-12088-7-git-send-email-bharata@linux.vnet.ibm.com> <20150504181059.5321ba37@thh440s> <20150506042809.GI18380@in.ibm.com> <20150506083203.44a34952@thh440s> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20150506083203.44a34952@thh440s> Subject: Re: [Qemu-devel] [RFC PATCH v3 06/24] spapr: Consolidate cpu init code into a routine Reply-To: bharata@linux.vnet.ibm.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Thomas Huth Cc: mdroth@linux.vnet.ibm.com, aik@ozlabs.ru, agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, tyreld@linux.vnet.ibm.com, imammedo@redhat.com, nfont@linux.vnet.ibm.com, afaerber@suse.de, david@gibson.dropbear.id.au On Wed, May 06, 2015 at 08:32:03AM +0200, Thomas Huth wrote: > On Wed, 6 May 2015 09:58:09 +0530 > Bharata B Rao wrote: > > > On Mon, May 04, 2015 at 06:10:59PM +0200, Thomas Huth wrote: > > > On Fri, 24 Apr 2015 12:17:28 +0530 > > > Bharata B Rao wrote: > > > > > > > Factor out bits of sPAPR specific CPU initialization code into > > > > a separate routine so that it can be called from CPU hotplug > > > > path too. > > > > > > > > Signed-off-by: Bharata B Rao > > > > Reviewed-by: David Gibson > > > > --- > > > > hw/ppc/spapr.c | 54 +++++++++++++++++++++++++++++------------------------- > > > > 1 file changed, 29 insertions(+), 25 deletions(-) > > > > > > > > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > > > > index a56f9a1..5c8f2ff 100644 > > > > --- a/hw/ppc/spapr.c > > > > +++ b/hw/ppc/spapr.c > > > > @@ -1440,6 +1440,34 @@ static void spapr_drc_reset(void *opaque) > > > > } > > > > } > > > > > > > > +static void spapr_cpu_init(PowerPCCPU *cpu) > > > > +{ > > > > + CPUPPCState *env = &cpu->env; > > > > + > > > > + /* Set time-base frequency to 512 MHz */ > > > > + cpu_ppc_tb_init(env, TIMEBASE_FREQ); > > > > + > > > > + /* PAPR always has exception vectors in RAM not ROM. To ensure this, > > > > + * MSR[IP] should never be set. > > > > + */ > > > > + env->msr_mask &= ~(1 << 6); > > > > > > While you're at it ... could we maybe get a proper #define for that MSR > > > bit? (just like the other ones in target-ppc/cpu.h) > > > > Sure will use MSR_EP here next time. > > According to the comment in cpu.h, the EP bit was for the 601 CPU only, > so I think it would be better to introduce a new #define MSR_IP 6 (or > so) here instead. Kernel defines bit 6 as #define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */ (arch/powerpc/include/asm/reg.h) QEMU defines it as #define MSR_EP 6 /* Exception prefix on 601 */ I can add MSR_IP in QEMU, but that will mean two defines for same bit position, but I think MSR_IP_LG in kernel or MSR_EP in QEMU both mean the same, but called differently. Regards, Bharata.