From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40710) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yqn1K-0007wp-4X for qemu-devel@nongnu.org; Fri, 08 May 2015 14:29:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yqn1G-00026k-R7 for qemu-devel@nongnu.org; Fri, 08 May 2015 14:29:10 -0400 Received: from out4-smtp.messagingengine.com ([66.111.4.28]:55307) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yqn1G-00025W-Lu for qemu-devel@nongnu.org; Fri, 08 May 2015 14:29:06 -0400 Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id 7F0DB20955 for ; Fri, 8 May 2015 14:29:04 -0400 (EDT) Date: Fri, 8 May 2015 14:29:47 -0400 From: "Emilio G. Cota" Message-ID: <20150508182947.GA9290@flamenco> References: <1430926687-25875-1-git-send-email-a.rigo@virtualopensystems.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1430926687-25875-1-git-send-email-a.rigo@virtualopensystems.com> Subject: Re: [Qemu-devel] [RFC 0/5] Slow-path for atomic instruction translation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alvise Rigo Cc: mttcg@listserver.greensocs.com, jani.kokkonen@huawei.com, tech@virtualopensystems.com, claudio.fontana@huawei.com, qemu-devel@nongnu.org On Wed, May 06, 2015 at 17:38:02 +0200, Alvise Rigo wrote: > This patch series provides an infrastructure for atomic > instruction implementation in QEMU, paving the way for TCG multi-threading. > The adopted design does not rely on host atomic > instructions and is intended to propose a 'legacy' solution for > translating guest atomic instructions. Patch 2 doesn't apply to current master. I fixed the conflict manually and get a segfault before it boots: (gdb) bt #0 0x0000555555657b04 in test_bit (addr=, nr=) at /local/home/cota/src/qemu/include/qemu/bitops.h:119 #1 cpu_physical_memory_excl_is_dirty (addr=18446744073709551615) at /local/home/cota/src/qemu/include/exec/ram_addr.h:214 #2 tlb_set_page_with_attrs (cpu=, vaddr=, paddr=503316480, attrs=..., prot=, mmu_idx=3, size=1024) at /local/home/cota/src/qemu/cputlb.c:328 #3 0x0000555555714c68 in arm_cpu_handle_mmu_fault (cs=0x555556334500, address=, access_type=0, mmu_idx=3) at /local/home/cota/src/qemu/target-arm/helper.c:5813 #4 0x00005555557077b0 in tlb_fill (cs=0x555556334500, addr=, is_write=, mmu_idx=, retaddr=140737065132893) at /local/home/cota/src/qemu/target-arm/op_helper.c:69 #5 0x000055555565939f in helper_le_ldul_mmu (env=0x55555633c750, addr=503316484, mmu_idx=3, retaddr=) at /local/home/cota/src/qemu/softmmu_template.h:192 #6 0x00007fffe6c623db in code_gen_buffer () #7 0x00005555556156ea in cpu_tb_exec ( tb_ptr=0x7fffe6c62320 "A\213n\374\205\355\017\205\207", cpu=0x555556334500) at /local/home/cota/src/qemu/cpu-exec.c:199 #8 cpu_arm_exec (env=0x55555633c750) at /local/home/cota/src/qemu/cpu-exec.c:519 #9 0x000055555563c340 in tcg_cpu_exec (env=0x55555633c750) at /local/home/cota/src/qemu/cpus.c:1354 #10 tcg_exec_all () at /local/home/cota/src/qemu/cpus.c:1387 #11 qemu_tcg_cpu_thread_fn (arg=) at /local/home/cota/src/qemu/cpus.c:1032 #12 0x00007ffff40dfe9a in start_thread (arg=0x7fffe4a45700) at pthread_create.c:308 #13 0x00007ffff3e0d38d in clone () at ../sysdeps/unix/sysv/linux/x86_64/clone.S:112 #14 0x0000000000000000 in ?? () It could be that my manual fix of the conflicts was wrong. What commit are your patches based on? Thanks, Emilio