From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57369) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yw4L3-0007wk-A9 for qemu-devel@nongnu.org; Sat, 23 May 2015 03:59:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yw4L0-0003zJ-Tc for qemu-devel@nongnu.org; Sat, 23 May 2015 03:59:21 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:33717) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yw4L0-0003xZ-O3 for qemu-devel@nongnu.org; Sat, 23 May 2015 03:59:18 -0400 Date: Sat, 23 May 2015 09:59:06 +0200 From: Aurelien Jarno Message-ID: <20150523075906.GA25414@aurel32.net> References: <1432243971-26417-1-git-send-email-aurelien@aurel32.net> <555E512F.4050603@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <555E512F.4050603@twiddle.net> Subject: Re: [Qemu-devel] [PATCH] target-s390x: fix LOAD MULTIPLE instruction on page boundary List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, Alexander Graf On 2015-05-21 14:42, Richard Henderson wrote: > On 05/21/2015 02:32 PM, Aurelien Jarno wrote: > > When consecutive memory locations are on page boundary a page fault > > might occur when using the LOAD MULTIPLE instruction. In that case real > > hardware doesn't load any register. > > > > This is an important detail in case the base register is in the list > > of registers to be loaded. If a page fault occurs this register might be > > overwritten and when the instruction is later restarted the wrong > > base register value is useD. > > > > Fix this by first loading all values from memory and then writing them > > back to the registers. > > > > This fixes random segmentation faults seen in the guest. > > > > Cc: Alexander Graf > > Cc: Richard Henderson > > Signed-off-by: Aurelien Jarno > > --- > > target-s390x/translate.c | 56 +++++++++++++++++++++++++++++++++++++++++++----- > > 1 file changed, 51 insertions(+), 5 deletions(-) > > Hmm. Seems to be un/under-specified in the PoO. That said, There is a small sentence in the PoO, in chapter "Program Execution", section "Sequence of Storage Reference": It can normally be assumed that the execution of each instruction occurs as an indivisible event. > Reviewed-by: Richard Henderson > > It would be nice to know if there ought to be similar up-front access checking > for STM, to avoid errant partial stores. I have just checked, the same is also true for STM instructions, though it's probably more difficult to fix that in QEMU. Maybe we need a way to check if a load/store will succeed, preferably without using a helper. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net