* [Qemu-devel] [PATCH v9 01/24] hw/acpi/aml-build: Make enum values to be upper case to match coding style
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
@ 2015-05-25 2:54 ` Shannon Zhao
2015-05-25 2:54 ` [Qemu-devel] [PATCH v9 02/24] hw/arm/virt: Move common definitions to virt.h Shannon Zhao
` (23 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:54 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 12 ++++----
hw/i386/acpi-build.c | 58 +++++++++++++++++++-------------------
include/hw/acpi/aml-build.h | 68 ++++++++++++++++++++++-----------------------
3 files changed, 69 insertions(+), 69 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 77ce00b..7a478ae 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -833,7 +833,7 @@ Aml *aml_word_bus_number(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
uint16_t addr_trans, uint16_t len)
{
- return aml_word_as_desc(aml_bus_number_range, min_fixed, max_fixed, dec,
+ return aml_word_as_desc(AML_BUS_NUMBER_RANGE, min_fixed, max_fixed, dec,
addr_gran, addr_min, addr_max, addr_trans, len, 0);
}
@@ -850,7 +850,7 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
uint16_t len)
{
- return aml_word_as_desc(aml_io_range, min_fixed, max_fixed, dec,
+ return aml_word_as_desc(AML_IO_RANGE, min_fixed, max_fixed, dec,
addr_gran, addr_min, addr_max, addr_trans, len,
isa_ranges);
}
@@ -862,7 +862,7 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
* ACPI 5.0: 19.5.34 DWordMemory (DWord Memory Resource Descriptor Macro)
*/
Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
- AmlMaxFixed max_fixed, AmlCacheble cacheable,
+ AmlMaxFixed max_fixed, AmlCacheable cacheable,
AmlReadAndWrite read_and_write,
uint32_t addr_gran, uint32_t addr_min,
uint32_t addr_max, uint32_t addr_trans,
@@ -870,7 +870,7 @@ Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
{
uint8_t flags = read_and_write | (cacheable << 1);
- return aml_dword_as_desc(aml_memory_range, min_fixed, max_fixed,
+ return aml_dword_as_desc(AML_MEMORY_RANGE, min_fixed, max_fixed,
dec, addr_gran, addr_min, addr_max,
addr_trans, len, flags);
}
@@ -882,7 +882,7 @@ Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
* ACPI 5.0: 19.5.102 QWordMemory (QWord Memory Resource Descriptor Macro)
*/
Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
- AmlMaxFixed max_fixed, AmlCacheble cacheable,
+ AmlMaxFixed max_fixed, AmlCacheable cacheable,
AmlReadAndWrite read_and_write,
uint64_t addr_gran, uint64_t addr_min,
uint64_t addr_max, uint64_t addr_trans,
@@ -890,7 +890,7 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
{
uint8_t flags = read_and_write | (cacheable << 1);
- return aml_qword_as_desc(aml_memory_range, min_fixed, max_fixed,
+ return aml_qword_as_desc(AML_MEMORY_RANGE, min_fixed, max_fixed,
dec, addr_gran, addr_min, addr_max,
addr_trans, len, flags);
}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 73259e7..c7c6b61 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -620,31 +620,31 @@ build_ssdt(GArray *table_data, GArray *linker,
/* build PCI0._CRS */
crs = aml_resource_template();
aml_append(crs,
- aml_word_bus_number(aml_min_fixed, aml_max_fixed, aml_pos_decode,
+ aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
0x0000, 0x0000, 0x00FF, 0x0000, 0x0100));
- aml_append(crs, aml_io(aml_decode16, 0x0CF8, 0x0CF8, 0x01, 0x08));
+ aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
+ aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_POS_DECODE, AML_ENTIRE_RANGE,
0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
aml_append(crs,
- aml_word_io(aml_min_fixed, aml_max_fixed,
- aml_pos_decode, aml_entire_range,
+ aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_POS_DECODE, AML_ENTIRE_RANGE,
0x0000, 0x0D00, 0xFFFF, 0x0000, 0xF300));
aml_append(crs,
- aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
- aml_cacheable, aml_ReadWrite,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_CACHEABLE, AML_READ_WRITE,
0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
aml_append(crs,
- aml_dword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
- aml_non_cacheable, aml_ReadWrite,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE,
0, pci->w32.begin, pci->w32.end - 1, 0,
pci->w32.end - pci->w32.begin));
if (pci->w64.begin) {
aml_append(crs,
- aml_qword_memory(aml_pos_decode, aml_min_fixed, aml_max_fixed,
- aml_cacheable, aml_ReadWrite,
+ aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_CACHEABLE, AML_READ_WRITE,
0, pci->w64.begin, pci->w64.end - 1, 0,
pci->w64.end - pci->w64.begin));
}
@@ -658,7 +658,7 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
crs = aml_resource_template();
aml_append(crs,
- aml_io(aml_decode16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
+ aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
);
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(scope, dev);
@@ -673,7 +673,7 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
crs = aml_resource_template();
aml_append(crs,
- aml_io(aml_decode16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
+ aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
pm->pcihp_io_len)
);
aml_append(dev, aml_name_decl("_CRS", crs));
@@ -720,7 +720,7 @@ build_ssdt(GArray *table_data, GArray *linker,
crs = aml_resource_template();
aml_append(crs,
- aml_io(aml_decode16, misc->applesmc_io_base, misc->applesmc_io_base,
+ aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
0x01, APPLESMC_MAX_DATA_LENGTH)
);
aml_append(crs, aml_irq_no_flags(6));
@@ -738,13 +738,13 @@ build_ssdt(GArray *table_data, GArray *linker,
crs = aml_resource_template();
aml_append(crs,
- aml_io(aml_decode16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
+ aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
);
aml_append(dev, aml_name_decl("_CRS", crs));
- aml_append(dev, aml_operation_region("PEOR", aml_system_io,
+ aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
misc->pvpanic_port, 1));
- field = aml_field("PEOR", aml_byte_acc, aml_preserve);
+ field = aml_field("PEOR", AML_BYTE_ACC, AML_PRESERVE);
aml_append(field, aml_named_field("PEPT", 8));
aml_append(dev, field);
@@ -773,15 +773,15 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
crs = aml_resource_template();
aml_append(crs,
- aml_io(aml_decode16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
+ aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
pm->cpu_hp_io_len)
);
aml_append(dev, aml_name_decl("_CRS", crs));
aml_append(sb_scope, dev);
/* declare CPU hotplug MMIO region and PRS field to access it */
aml_append(sb_scope, aml_operation_region(
- "PRST", aml_system_io, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
- field = aml_field("PRST", aml_byte_acc, aml_preserve);
+ "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
+ field = aml_field("PRST", AML_BYTE_ACC, AML_PRESERVE);
aml_append(field, aml_named_field("PRS", 256));
aml_append(sb_scope, field);
@@ -845,18 +845,18 @@ build_ssdt(GArray *table_data, GArray *linker,
crs = aml_resource_template();
aml_append(crs,
- aml_io(aml_decode16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
+ aml_io(AML_DECODE16, pm->mem_hp_io_base, pm->mem_hp_io_base, 0,
pm->mem_hp_io_len)
);
aml_append(scope, aml_name_decl("_CRS", crs));
aml_append(scope, aml_operation_region(
- stringify(MEMORY_HOTPLUG_IO_REGION), aml_system_io,
+ stringify(MEMORY_HOTPLUG_IO_REGION), AML_SYSTEM_IO,
pm->mem_hp_io_base, pm->mem_hp_io_len)
);
- field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc,
- aml_preserve);
+ field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
+ AML_PRESERVE);
aml_append(field, /* read only */
aml_named_field(stringify(MEMORY_SLOT_ADDR_LOW), 32));
aml_append(field, /* read only */
@@ -869,8 +869,8 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_named_field(stringify(MEMORY_SLOT_PROXIMITY), 32));
aml_append(scope, field);
- field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_byte_acc,
- aml_write_as_zeros);
+ field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_BYTE_ACC,
+ AML_WRITE_AS_ZEROS);
aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
aml_append(field, /* 1 if enabled, read only */
aml_named_field(stringify(MEMORY_SLOT_ENABLED), 1));
@@ -885,8 +885,8 @@ build_ssdt(GArray *table_data, GArray *linker,
aml_named_field(stringify(MEMORY_SLOT_EJECT), 1));
aml_append(scope, field);
- field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), aml_dword_acc,
- aml_preserve);
+ field = aml_field(stringify(MEMORY_HOTPLUG_IO_REGION), AML_DWORD_ACC,
+ AML_PRESERVE);
aml_append(field, /* DIMM selector, write only */
aml_named_field(stringify(MEMORY_SLOT_SLECTOR), 32));
aml_append(field, /* _OST event code, write only */
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 3947201..c0e81d4 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -36,49 +36,49 @@ struct Aml {
typedef struct Aml Aml;
typedef enum {
- aml_decode10 = 0,
- aml_decode16 = 1,
+ AML_DECODE10 = 0,
+ AML_DECODE16 = 1,
} AmlIODecode;
typedef enum {
- aml_any_acc = 0,
- aml_byte_acc = 1,
- aml_word_acc = 2,
- aml_dword_acc = 3,
- aml_qword_acc = 4,
- aml_buffer_acc = 5,
+ AML_ANY_ACC = 0,
+ AML_BYTE_ACC = 1,
+ AML_WORD_ACC = 2,
+ AML_DWORD_ACC = 3,
+ AML_QWORD_ACC = 4,
+ AML_BUFFER_ACC = 5,
} AmlAccessType;
typedef enum {
- aml_preserve = 0,
- aml_write_as_ones = 1,
- aml_write_as_zeros = 2,
+ AML_PRESERVE = 0,
+ AML_WRITE_AS_ONES = 1,
+ AML_WRITE_AS_ZEROS = 2,
} AmlUpdateRule;
typedef enum {
- aml_system_memory = 0x00,
- aml_system_io = 0x01,
+ AML_SYSTEM_MEMORY = 0X00,
+ AML_SYSTEM_IO = 0X01,
} AmlRegionSpace;
typedef enum {
- aml_memory_range = 0,
- aml_io_range = 1,
- aml_bus_number_range = 2,
+ AML_MEMORY_RANGE = 0,
+ AML_IO_RANGE = 1,
+ AML_BUS_NUMBER_RANGE = 2,
} AmlResourceType;
typedef enum {
- aml_sub_decode = 1 << 1,
- aml_pos_decode = 0
+ AML_SUB_DECODE = 1 << 1,
+ AML_POS_DECODE = 0
} AmlDecode;
typedef enum {
- aml_max_fixed = 1 << 3,
- aml_max_not_fixed = 0,
+ AML_MAX_FIXED = 1 << 3,
+ AML_MAX_NOT_FIXED = 0,
} AmlMaxFixed;
typedef enum {
- aml_min_fixed = 1 << 2,
- aml_min_not_fixed = 0
+ AML_MIN_FIXED = 1 << 2,
+ AML_MIN_NOT_FIXED = 0
} AmlMinFixed;
/*
@@ -86,9 +86,9 @@ typedef enum {
* _RNG field definition
*/
typedef enum {
- aml_isa_only = 1,
- aml_non_isa_only = 2,
- aml_entire_range = 3,
+ AML_ISA_ONLY = 1,
+ AML_NON_ISA_ONLY = 2,
+ AML_ENTIRE_RANGE = 3,
} AmlISARanges;
/*
@@ -96,19 +96,19 @@ typedef enum {
* _MEM field definition
*/
typedef enum {
- aml_non_cacheable = 0,
- aml_cacheable = 1,
- aml_write_combining = 2,
- aml_prefetchable = 3,
-} AmlCacheble;
+ AML_NON_CACHEABLE = 0,
+ AML_CACHEABLE = 1,
+ AML_WRITE_COMBINING = 2,
+ AML_PREFETCHABLE = 3,
+} AmlCacheable;
/*
* ACPI 1.0b: Table 6-25 Memory Resource Flag (Resource Type = 0) Definitions
* _RW field definition
*/
typedef enum {
- aml_ReadOnly = 0,
- aml_ReadWrite = 1,
+ AML_READ_ONLY = 0,
+ AML_READ_WRITE = 1,
} AmlReadAndWrite;
typedef
@@ -191,13 +191,13 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
uint16_t addr_max, uint16_t addr_trans,
uint16_t len);
Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
- AmlMaxFixed max_fixed, AmlCacheble cacheable,
+ AmlMaxFixed max_fixed, AmlCacheable cacheable,
AmlReadAndWrite read_and_write,
uint32_t addr_gran, uint32_t addr_min,
uint32_t addr_max, uint32_t addr_trans,
uint32_t len);
Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
- AmlMaxFixed max_fixed, AmlCacheble cacheable,
+ AmlMaxFixed max_fixed, AmlCacheable cacheable,
AmlReadAndWrite read_and_write,
uint64_t addr_gran, uint64_t addr_min,
uint64_t addr_max, uint64_t addr_trans,
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 02/24] hw/arm/virt: Move common definitions to virt.h
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
2015-05-25 2:54 ` [Qemu-devel] [PATCH v9 01/24] hw/acpi/aml-build: Make enum values to be upper case to match coding style Shannon Zhao
@ 2015-05-25 2:54 ` Shannon Zhao
2015-05-27 8:07 ` Alex Bennée
2015-05-25 2:54 ` [Qemu-devel] [PATCH v9 03/24] hw/arm/virt: Record PCIe ranges in MemMapEntry array Shannon Zhao
` (22 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:54 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Move some common definitions to virt.h. These will be used by
generating ACPI tables.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt.c | 21 +------------------
include/hw/arm/virt.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 57 insertions(+), 20 deletions(-)
create mode 100644 include/hw/arm/virt.h
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a7f9a10..8959d0c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -31,6 +31,7 @@
#include "hw/sysbus.h"
#include "hw/arm/arm.h"
#include "hw/arm/primecell.h"
+#include "hw/arm/virt.h"
#include "hw/devices.h"
#include "net/net.h"
#include "sysemu/block-backend.h"
@@ -44,8 +45,6 @@
#include "qemu/error-report.h"
#include "hw/pci-host/gpex.h"
-#define NUM_VIRTIO_TRANSPORTS 32
-
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 128
@@ -60,24 +59,6 @@
#define GIC_FDT_IRQ_PPI_CPU_START 8
#define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
-enum {
- VIRT_FLASH,
- VIRT_MEM,
- VIRT_CPUPERIPHS,
- VIRT_GIC_DIST,
- VIRT_GIC_CPU,
- VIRT_UART,
- VIRT_MMIO,
- VIRT_RTC,
- VIRT_FW_CFG,
- VIRT_PCIE,
-};
-
-typedef struct MemMapEntry {
- hwaddr base;
- hwaddr size;
-} MemMapEntry;
-
typedef struct VirtBoardInfo {
struct arm_boot_info bootinfo;
const char *cpu_model;
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
new file mode 100644
index 0000000..2fe0d2e
--- /dev/null
+++ b/include/hw/arm/virt.h
@@ -0,0 +1,56 @@
+/*
+ *
+ * Copyright (c) 2015 Linaro Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Emulate a virtual board which works by passing Linux all the information
+ * it needs about what devices are present via the device tree.
+ * There are some restrictions about what we can do here:
+ * + we can only present devices whose Linux drivers will work based
+ * purely on the device tree with no platform data at all
+ * + we want to present a very stripped-down minimalist platform,
+ * both because this reduces the security attack surface from the guest
+ * and also because it reduces our exposure to being broken when
+ * the kernel updates its device tree bindings and requires further
+ * information in a device binding that we aren't providing.
+ * This is essentially the same approach kvmtool uses.
+ */
+
+#ifndef QEMU_ARM_VIRT_H
+#define QEMU_ARM_VIRT_H
+
+#include "qemu-common.h"
+
+#define NUM_VIRTIO_TRANSPORTS 32
+
+enum {
+ VIRT_FLASH,
+ VIRT_MEM,
+ VIRT_CPUPERIPHS,
+ VIRT_GIC_DIST,
+ VIRT_GIC_CPU,
+ VIRT_UART,
+ VIRT_MMIO,
+ VIRT_RTC,
+ VIRT_FW_CFG,
+ VIRT_PCIE,
+};
+
+typedef struct MemMapEntry {
+ hwaddr base;
+ hwaddr size;
+} MemMapEntry;
+
+
+#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 02/24] hw/arm/virt: Move common definitions to virt.h
2015-05-25 2:54 ` [Qemu-devel] [PATCH v9 02/24] hw/arm/virt: Move common definitions to virt.h Shannon Zhao
@ 2015-05-27 8:07 ` Alex Bennée
0 siblings, 0 replies; 53+ messages in thread
From: Alex Bennée @ 2015-05-27 8:07 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, imammedo, pbonzini,
lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Move some common definitions to virt.h. These will be used by
> generating ACPI tables.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/arm/virt.c | 21 +------------------
> include/hw/arm/virt.h | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 57 insertions(+), 20 deletions(-)
> create mode 100644 include/hw/arm/virt.h
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index a7f9a10..8959d0c 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -31,6 +31,7 @@
> #include "hw/sysbus.h"
> #include "hw/arm/arm.h"
> #include "hw/arm/primecell.h"
> +#include "hw/arm/virt.h"
> #include "hw/devices.h"
> #include "net/net.h"
> #include "sysemu/block-backend.h"
> @@ -44,8 +45,6 @@
> #include "qemu/error-report.h"
> #include "hw/pci-host/gpex.h"
>
> -#define NUM_VIRTIO_TRANSPORTS 32
> -
> /* Number of external interrupt lines to configure the GIC with */
> #define NUM_IRQS 128
>
> @@ -60,24 +59,6 @@
> #define GIC_FDT_IRQ_PPI_CPU_START 8
> #define GIC_FDT_IRQ_PPI_CPU_WIDTH 8
>
> -enum {
> - VIRT_FLASH,
> - VIRT_MEM,
> - VIRT_CPUPERIPHS,
> - VIRT_GIC_DIST,
> - VIRT_GIC_CPU,
> - VIRT_UART,
> - VIRT_MMIO,
> - VIRT_RTC,
> - VIRT_FW_CFG,
> - VIRT_PCIE,
> -};
> -
> -typedef struct MemMapEntry {
> - hwaddr base;
> - hwaddr size;
> -} MemMapEntry;
> -
> typedef struct VirtBoardInfo {
> struct arm_boot_info bootinfo;
> const char *cpu_model;
> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
> new file mode 100644
> index 0000000..2fe0d2e
> --- /dev/null
> +++ b/include/hw/arm/virt.h
> @@ -0,0 +1,56 @@
> +/*
> + *
> + * Copyright (c) 2015 Linaro Limited
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms and conditions of the GNU General Public License,
> + * version 2 or later, as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + *
> + * Emulate a virtual board which works by passing Linux all the information
> + * it needs about what devices are present via the device tree.
> + * There are some restrictions about what we can do here:
> + * + we can only present devices whose Linux drivers will work based
> + * purely on the device tree with no platform data at all
> + * + we want to present a very stripped-down minimalist platform,
> + * both because this reduces the security attack surface from the guest
> + * and also because it reduces our exposure to being broken when
> + * the kernel updates its device tree bindings and requires further
> + * information in a device binding that we aren't providing.
> + * This is essentially the same approach kvmtool uses.
> + */
> +
> +#ifndef QEMU_ARM_VIRT_H
> +#define QEMU_ARM_VIRT_H
> +
> +#include "qemu-common.h"
> +
> +#define NUM_VIRTIO_TRANSPORTS 32
> +
> +enum {
> + VIRT_FLASH,
> + VIRT_MEM,
> + VIRT_CPUPERIPHS,
> + VIRT_GIC_DIST,
> + VIRT_GIC_CPU,
> + VIRT_UART,
> + VIRT_MMIO,
> + VIRT_RTC,
> + VIRT_FW_CFG,
> + VIRT_PCIE,
> +};
> +
> +typedef struct MemMapEntry {
> + hwaddr base;
> + hwaddr size;
> +} MemMapEntry;
> +
> +
> +#endif
--
Alex Bennée
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 03/24] hw/arm/virt: Record PCIe ranges in MemMapEntry array
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
2015-05-25 2:54 ` [Qemu-devel] [PATCH v9 01/24] hw/acpi/aml-build: Make enum values to be upper case to match coding style Shannon Zhao
2015-05-25 2:54 ` [Qemu-devel] [PATCH v9 02/24] hw/arm/virt: Move common definitions to virt.h Shannon Zhao
@ 2015-05-25 2:54 ` Shannon Zhao
2015-05-27 8:17 ` Alex Bennée
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 04/24] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM Shannon Zhao
` (21 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:54 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
To generate ACPI table for PCIe controller, we need the base and size of
the PCIe ranges. Record these ranges in MemMapEntry array, then we could
share and use them for generating ACPI table.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt.c | 37 +++++++++++++------------------------
include/hw/arm/virt.h | 3 +++
2 files changed, 16 insertions(+), 24 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 8959d0c..250b9bc 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -112,14 +112,9 @@ static const MemMapEntry a15memmap[] = {
[VIRT_FW_CFG] = { 0x09020000, 0x0000000a },
[VIRT_MMIO] = { 0x0a000000, 0x00000200 },
/* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
- /*
- * PCIE verbose map:
- *
- * MMIO window { 0x10000000, 0x2eff0000 },
- * PIO window { 0x3eff0000, 0x00010000 },
- * ECAM { 0x3f000000, 0x01000000 },
- */
- [VIRT_PCIE] = { 0x10000000, 0x30000000 },
+ [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
+ [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
+ [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
[VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
};
@@ -625,16 +620,14 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
uint32_t gic_phandle)
{
- hwaddr base = vbi->memmap[VIRT_PCIE].base;
- hwaddr size = vbi->memmap[VIRT_PCIE].size;
- hwaddr end = base + size;
- hwaddr size_mmio;
- hwaddr size_ioport = 64 * 1024;
- int nr_pcie_buses = 16;
- hwaddr size_ecam = PCIE_MMCFG_SIZE_MIN * nr_pcie_buses;
- hwaddr base_mmio = base;
- hwaddr base_ioport;
- hwaddr base_ecam;
+ hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base;
+ hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size;
+ hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base;
+ hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size;
+ hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base;
+ hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size;
+ hwaddr base = base_mmio;
+ int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
int irq = vbi->irqmap[VIRT_PCIE];
MemoryRegion *mmio_alias;
MemoryRegion *mmio_reg;
@@ -644,10 +637,6 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
char *nodename;
int i;
- base_ecam = QEMU_ALIGN_DOWN(end - size_ecam, size_ecam);
- base_ioport = QEMU_ALIGN_DOWN(base_ecam - size_ioport, size_ioport);
- size_mmio = base_ioport - base;
-
dev = qdev_create(NULL, TYPE_GPEX_HOST);
qdev_init_nofail(dev);
@@ -670,7 +659,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
/* Map IO port space */
- sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_ioport);
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
for (i = 0; i < GPEX_NUM_IRQS; i++) {
sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
@@ -690,7 +679,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
2, base_ecam, 2, size_ecam);
qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
1, FDT_PCI_RANGE_IOPORT, 2, 0,
- 2, base_ioport, 2, size_ioport,
+ 2, base_pio, 2, size_pio,
1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
2, base_mmio, 2, size_mmio);
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 2fe0d2e..49a85cc 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -45,6 +45,9 @@ enum {
VIRT_RTC,
VIRT_FW_CFG,
VIRT_PCIE,
+ VIRT_PCIE_MMIO,
+ VIRT_PCIE_PIO,
+ VIRT_PCIE_ECAM,
};
typedef struct MemMapEntry {
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 03/24] hw/arm/virt: Record PCIe ranges in MemMapEntry array
2015-05-25 2:54 ` [Qemu-devel] [PATCH v9 03/24] hw/arm/virt: Record PCIe ranges in MemMapEntry array Shannon Zhao
@ 2015-05-27 8:17 ` Alex Bennée
2015-05-27 8:43 ` Shannon Zhao
0 siblings, 1 reply; 53+ messages in thread
From: Alex Bennée @ 2015-05-27 8:17 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, imammedo, pbonzini,
lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> To generate ACPI table for PCIe controller, we need the base and size of
> the PCIe ranges. Record these ranges in MemMapEntry array, then we could
> share and use them for generating ACPI table.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt.c | 37 +++++++++++++------------------------
> include/hw/arm/virt.h | 3 +++
> 2 files changed, 16 insertions(+), 24 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 8959d0c..250b9bc 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -112,14 +112,9 @@ static const MemMapEntry a15memmap[] = {
> [VIRT_FW_CFG] = { 0x09020000, 0x0000000a },
> [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
> /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
> - /*
> - * PCIE verbose map:
> - *
> - * MMIO window { 0x10000000, 0x2eff0000 },
> - * PIO window { 0x3eff0000, 0x00010000 },
> - * ECAM { 0x3f000000, 0x01000000 },
> - */
> - [VIRT_PCIE] = { 0x10000000, 0x30000000 },
> + [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
> + [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
> + [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
> [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
> };
>
> @@ -625,16 +620,14 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
> static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
> uint32_t gic_phandle)
> {
> - hwaddr base = vbi->memmap[VIRT_PCIE].base;
> - hwaddr size = vbi->memmap[VIRT_PCIE].size;
> - hwaddr end = base + size;
> - hwaddr size_mmio;
> - hwaddr size_ioport = 64 * 1024;
> - int nr_pcie_buses = 16;
> - hwaddr size_ecam = PCIE_MMCFG_SIZE_MIN * nr_pcie_buses;
> - hwaddr base_mmio = base;
> - hwaddr base_ioport;
> - hwaddr base_ecam;
> + hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base;
> + hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size;
> + hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base;
> + hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size;
> + hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base;
> + hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size;
> + hwaddr base = base_mmio;
> + int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
> int irq = vbi->irqmap[VIRT_PCIE];
> MemoryRegion *mmio_alias;
> MemoryRegion *mmio_reg;
> @@ -644,10 +637,6 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
> char *nodename;
> int i;
>
> - base_ecam = QEMU_ALIGN_DOWN(end - size_ecam, size_ecam);
> - base_ioport = QEMU_ALIGN_DOWN(base_ecam - size_ioport, size_ioport);
> - size_mmio = base_ioport - base;
> -
> dev = qdev_create(NULL, TYPE_GPEX_HOST);
> qdev_init_nofail(dev);
>
> @@ -670,7 +659,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
> memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
>
> /* Map IO port space */
> - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_ioport);
> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
>
> for (i = 0; i < GPEX_NUM_IRQS; i++) {
> sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
> @@ -690,7 +679,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
> 2, base_ecam, 2, size_ecam);
> qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
> 1, FDT_PCI_RANGE_IOPORT, 2, 0,
> - 2, base_ioport, 2, size_ioport,
> + 2, base_pio, 2, size_pio,
> 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
> 2, base_mmio, 2, size_mmio);
>
> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
> index 2fe0d2e..49a85cc 100644
> --- a/include/hw/arm/virt.h
> +++ b/include/hw/arm/virt.h
> @@ -45,6 +45,9 @@ enum {
> VIRT_RTC,
> VIRT_FW_CFG,
> VIRT_PCIE,
> + VIRT_PCIE_MMIO,
> + VIRT_PCIE_PIO,
> + VIRT_PCIE_ECAM,
> };
We could probably do with some comments with the enum as to what the
different types of VIRT_PCIE* are. I can guess at MMIO and PIO but
without being overly familiar with PCIe what is ECAM?
And this patch removes the VIRT_PCIE regions to replace with
MMIO/PIO/EMAC regions but we still have a VIRT_PCIE irq. I think this implies
the the MMIO/PIO/ECAM regions are just sub-regions of the device which
has the one IRQ but a decent comment making this explicit would help
understanding (especially for someone not super familiar with the PCIe
spec ;-)
Cheers,
--
Alex Bennée
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 03/24] hw/arm/virt: Record PCIe ranges in MemMapEntry array
2015-05-27 8:17 ` Alex Bennée
@ 2015-05-27 8:43 ` Shannon Zhao
0 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-27 8:43 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, imammedo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/5/27 16:17, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> To generate ACPI table for PCIe controller, we need the base and size of
>> the PCIe ranges. Record these ranges in MemMapEntry array, then we could
>> share and use them for generating ACPI table.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/arm/virt.c | 37 +++++++++++++------------------------
>> include/hw/arm/virt.h | 3 +++
>> 2 files changed, 16 insertions(+), 24 deletions(-)
>>
>> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
>> index 8959d0c..250b9bc 100644
>> --- a/hw/arm/virt.c
>> +++ b/hw/arm/virt.c
>> @@ -112,14 +112,9 @@ static const MemMapEntry a15memmap[] = {
>> [VIRT_FW_CFG] = { 0x09020000, 0x0000000a },
>> [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
>> /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
>> - /*
>> - * PCIE verbose map:
>> - *
>> - * MMIO window { 0x10000000, 0x2eff0000 },
>> - * PIO window { 0x3eff0000, 0x00010000 },
>> - * ECAM { 0x3f000000, 0x01000000 },
>> - */
>> - [VIRT_PCIE] = { 0x10000000, 0x30000000 },
>> + [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
>> + [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
>> + [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
>> [VIRT_MEM] = { 0x40000000, 30ULL * 1024 * 1024 * 1024 },
>> };
>>
>> @@ -625,16 +620,14 @@ static void create_pcie_irq_map(const VirtBoardInfo *vbi, uint32_t gic_phandle,
>> static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
>> uint32_t gic_phandle)
>> {
>> - hwaddr base = vbi->memmap[VIRT_PCIE].base;
>> - hwaddr size = vbi->memmap[VIRT_PCIE].size;
>> - hwaddr end = base + size;
>> - hwaddr size_mmio;
>> - hwaddr size_ioport = 64 * 1024;
>> - int nr_pcie_buses = 16;
>> - hwaddr size_ecam = PCIE_MMCFG_SIZE_MIN * nr_pcie_buses;
>> - hwaddr base_mmio = base;
>> - hwaddr base_ioport;
>> - hwaddr base_ecam;
>> + hwaddr base_mmio = vbi->memmap[VIRT_PCIE_MMIO].base;
>> + hwaddr size_mmio = vbi->memmap[VIRT_PCIE_MMIO].size;
>> + hwaddr base_pio = vbi->memmap[VIRT_PCIE_PIO].base;
>> + hwaddr size_pio = vbi->memmap[VIRT_PCIE_PIO].size;
>> + hwaddr base_ecam = vbi->memmap[VIRT_PCIE_ECAM].base;
>> + hwaddr size_ecam = vbi->memmap[VIRT_PCIE_ECAM].size;
>> + hwaddr base = base_mmio;
>> + int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
>> int irq = vbi->irqmap[VIRT_PCIE];
>> MemoryRegion *mmio_alias;
>> MemoryRegion *mmio_reg;
>> @@ -644,10 +637,6 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
>> char *nodename;
>> int i;
>>
>> - base_ecam = QEMU_ALIGN_DOWN(end - size_ecam, size_ecam);
>> - base_ioport = QEMU_ALIGN_DOWN(base_ecam - size_ioport, size_ioport);
>> - size_mmio = base_ioport - base;
>> -
>> dev = qdev_create(NULL, TYPE_GPEX_HOST);
>> qdev_init_nofail(dev);
>>
>> @@ -670,7 +659,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
>> memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
>>
>> /* Map IO port space */
>> - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_ioport);
>> + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
>>
>> for (i = 0; i < GPEX_NUM_IRQS; i++) {
>> sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
>> @@ -690,7 +679,7 @@ static void create_pcie(const VirtBoardInfo *vbi, qemu_irq *pic,
>> 2, base_ecam, 2, size_ecam);
>> qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "ranges",
>> 1, FDT_PCI_RANGE_IOPORT, 2, 0,
>> - 2, base_ioport, 2, size_ioport,
>> + 2, base_pio, 2, size_pio,
>> 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
>> 2, base_mmio, 2, size_mmio);
>>
>> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
>> index 2fe0d2e..49a85cc 100644
>> --- a/include/hw/arm/virt.h
>> +++ b/include/hw/arm/virt.h
>> @@ -45,6 +45,9 @@ enum {
>> VIRT_RTC,
>> VIRT_FW_CFG,
>> VIRT_PCIE,
>> + VIRT_PCIE_MMIO,
>> + VIRT_PCIE_PIO,
>> + VIRT_PCIE_ECAM,
>> };
>
> We could probably do with some comments with the enum as to what the
> different types of VIRT_PCIE* are. I can guess at MMIO and PIO but
> without being overly familiar with PCIe what is ECAM?
>
I guess it's unnecessary to do that. These can be understood from the
literal meaning. If someone who is not familiar with PCIe, maybe Google
would give the answer.
> And this patch removes the VIRT_PCIE regions to replace with
> MMIO/PIO/EMAC regions but we still have a VIRT_PCIE irq. I think this implies
> the the MMIO/PIO/ECAM regions are just sub-regions of the device which
> has the one IRQ but a decent comment making this explicit would help
> understanding (especially for someone not super familiar with the PCIe
> spec ;-)
>
> Cheers,
>
--
Shannon
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 04/24] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (2 preceding siblings ...)
2015-05-25 2:54 ` [Qemu-devel] [PATCH v9 03/24] hw/arm/virt: Record PCIe ranges in MemMapEntry array Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 05/24] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
` (20 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Introduce a preliminary framework in virt-acpi-build.c with the main
ACPI build functions. It exposes the generated ACPI contents to
guest over fw_cfg.
The required ACPI v5.1 tables for ARM are:
- RSDP: Initial table that points to XSDT
- RSDT: Points to FADT GTDT MADT tables
- FADT: Generic information about the machine
- GTDT: Generic timer description table
- MADT: Multiple APIC description table
- DSDT: Holds all information about system devices/peripherals, pointed by FADT
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/arm/Makefile.objs | 1 +
hw/arm/virt-acpi-build.c | 182 +++++++++++++++++++++++++++++++++++++++
include/hw/arm/virt-acpi-build.h | 41 +++++++++
qemu-options.hx | 2 +-
trace-events | 3 +
5 files changed, 228 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/virt-acpi-build.c
create mode 100644 include/hw/arm/virt-acpi-build.h
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index a75a182..4b09caf 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -3,6 +3,7 @@ obj-$(CONFIG_DIGIC) += digic_boards.o
obj-y += integratorcp.o kzm.o mainstone.o musicpal.o nseries.o
obj-y += omap_sx1.o palm.o realview.o spitz.o stellaris.o
obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
+obj-$(CONFIG_ACPI) += virt-acpi-build.o
obj-y += netduino2.o
obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
new file mode 100644
index 0000000..b8a5bd8
--- /dev/null
+++ b/hw/arm/virt-acpi-build.c
@@ -0,0 +1,182 @@
+/* Support for generating ACPI tables and passing them to Guests
+ *
+ * ARM virt ACPI generation
+ *
+ * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
+ * Copyright (C) 2006 Fabrice Bellard
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
+ *
+ * Author: Shannon Zhao <zhaoshenglong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu-common.h"
+#include "hw/arm/virt-acpi-build.h"
+#include "qemu/bitmap.h"
+#include "trace.h"
+#include "qom/cpu.h"
+#include "target-arm/cpu.h"
+#include "hw/acpi/acpi-defs.h"
+#include "hw/acpi/acpi.h"
+#include "hw/nvram/fw_cfg.h"
+#include "hw/acpi/bios-linker-loader.h"
+#include "hw/loader.h"
+#include "hw/hw.h"
+#include "hw/acpi/aml-build.h"
+
+typedef
+struct AcpiBuildState {
+ /* Copy of table in RAM (for patching). */
+ MemoryRegion *table_mr;
+ MemoryRegion *rsdp_mr;
+ MemoryRegion *linker_mr;
+ /* Is table patched? */
+ bool patched;
+ VirtGuestInfo *guest_info;
+} AcpiBuildState;
+
+static
+void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
+{
+ GArray *table_offsets;
+
+ table_offsets = g_array_new(false, true /* clear */,
+ sizeof(uint32_t));
+
+ bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
+ 64, false /* high memory */);
+
+ /*
+ * The ACPI v5.1 tables for Hardware-reduced ACPI platform are:
+ * RSDP
+ * RSDT
+ * FADT
+ * GTDT
+ * MADT
+ * DSDT
+ */
+
+ /* Cleanup memory that's no longer used. */
+ g_array_free(table_offsets, true);
+}
+
+static void acpi_ram_update(MemoryRegion *mr, GArray *data)
+{
+ uint32_t size = acpi_data_len(data);
+
+ /* Make sure RAM size is correct - in case it got changed
+ * e.g. by migration */
+ memory_region_ram_resize(mr, size, &error_abort);
+
+ memcpy(memory_region_get_ram_ptr(mr), data->data, size);
+ memory_region_set_dirty(mr, 0, size);
+}
+
+static void virt_acpi_build_update(void *build_opaque, uint32_t offset)
+{
+ AcpiBuildState *build_state = build_opaque;
+ AcpiBuildTables tables;
+
+ /* No state to update or already patched? Nothing to do. */
+ if (!build_state || build_state->patched) {
+ return;
+ }
+ build_state->patched = true;
+
+ acpi_build_tables_init(&tables);
+
+ virt_acpi_build(build_state->guest_info, &tables);
+
+ acpi_ram_update(build_state->table_mr, tables.table_data);
+ acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
+ acpi_ram_update(build_state->linker_mr, tables.linker);
+
+
+ acpi_build_tables_cleanup(&tables, true);
+}
+
+static void virt_acpi_build_reset(void *build_opaque)
+{
+ AcpiBuildState *build_state = build_opaque;
+ build_state->patched = false;
+}
+
+static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
+ GArray *blob, const char *name,
+ uint64_t max_size)
+{
+ return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
+ name, virt_acpi_build_update, build_state);
+}
+
+static const VMStateDescription vmstate_virt_acpi_build = {
+ .name = "virt_acpi_build",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_BOOL(patched, AcpiBuildState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+void virt_acpi_setup(VirtGuestInfo *guest_info)
+{
+ AcpiBuildTables tables;
+ AcpiBuildState *build_state;
+
+ if (!guest_info->fw_cfg) {
+ trace_virt_acpi_setup();
+ return;
+ }
+
+ if (!acpi_enabled) {
+ trace_virt_acpi_setup();
+ return;
+ }
+
+ build_state = g_malloc0(sizeof *build_state);
+ build_state->guest_info = guest_info;
+
+ acpi_build_tables_init(&tables);
+ virt_acpi_build(build_state->guest_info, &tables);
+
+ /* Now expose it all to Guest */
+ build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
+ ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_MAX_SIZE);
+ assert(build_state->table_mr != NULL);
+
+ build_state->linker_mr =
+ acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
+
+ fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
+ tables.tcpalog->data, acpi_data_len(tables.tcpalog));
+
+ build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
+ ACPI_BUILD_RSDP_FILE, 0);
+
+ qemu_register_reset(virt_acpi_build_reset, build_state);
+ virt_acpi_build_reset(build_state);
+ vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
+
+ /* Cleanup tables but don't free the memory: we track it
+ * in build_state.
+ */
+ acpi_build_tables_cleanup(&tables, false);
+}
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
new file mode 100644
index 0000000..ff00121
--- /dev/null
+++ b/include/hw/arm/virt-acpi-build.h
@@ -0,0 +1,41 @@
+/*
+ *
+ * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
+ *
+ * Author: Shannon Zhao <zhaoshenglong@huawei.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2 or later, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_VIRT_ACPI_BUILD_H
+#define QEMU_VIRT_ACPI_BUILD_H
+
+#include "qemu-common.h"
+#include "hw/arm/virt.h"
+
+typedef struct VirtGuestInfo {
+ int smp_cpus;
+ FWCfgState *fw_cfg;
+ const MemMapEntry *memmap;
+ const int *irqmap;
+} VirtGuestInfo;
+
+
+typedef struct VirtGuestInfoState {
+ VirtGuestInfo info;
+ Notifier machine_done;
+} VirtGuestInfoState;
+
+void virt_acpi_setup(VirtGuestInfo *guest_info);
+
+#endif
diff --git a/qemu-options.hx b/qemu-options.hx
index ec356f6..030c14f 100644
--- a/qemu-options.hx
+++ b/qemu-options.hx
@@ -1352,7 +1352,7 @@ be needed to boot from old floppy disks.
ETEXI
DEF("no-acpi", 0, QEMU_OPTION_no_acpi,
- "-no-acpi disable ACPI\n", QEMU_ARCH_I386)
+ "-no-acpi disable ACPI\n", QEMU_ARCH_I386 | QEMU_ARCH_ARM)
STEXI
@item -no-acpi
@findex -no-acpi
diff --git a/trace-events b/trace-events
index 11387c3..3bb1f04 100644
--- a/trace-events
+++ b/trace-events
@@ -1594,3 +1594,6 @@ i8257_unregistered_dma(int nchan, int dma_pos, int dma_len) "unregistered DMA ch
cpu_set_state(int cpu_index, uint8_t state) "setting cpu %d state to %" PRIu8
cpu_halt(int cpu_index) "halting cpu %d"
cpu_unhalt(int cpu_index) "unhalting cpu %d"
+
+# hw/arm/virt-acpi-build.c
+virt_acpi_setup(void) "No fw cfg or ACPI disabled. Bailing out."
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 05/24] hw/acpi/aml-build: Add aml_memory32_fixed() term
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (3 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 04/24] hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARM Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 06/24] hw/acpi/aml-build: Add aml_interrupt() term Shannon Zhao
` (19 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Add aml_memory32_fixed() for describing device mmio region in resource
template. These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
---
hw/acpi/aml-build.c | 28 ++++++++++++++++++++++++++++
include/hw/acpi/aml-build.h | 2 ++
2 files changed, 30 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 7a478ae..ad4d7ea 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -26,6 +26,7 @@
#include <string.h>
#include "hw/acpi/aml-build.h"
#include "qemu/bswap.h"
+#include "qemu/bitops.h"
#include "hw/acpi/bios-linker-loader.h"
static GArray *build_alloc_array(void)
@@ -505,6 +506,33 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
return var;
}
+/*
+ * ACPI 1.0b: 6.4.3.4 32-Bit Fixed Location Memory Range Descriptor
+ * (Type 1, Large Item Name 0x6)
+ */
+Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
+ AmlReadAndWrite read_and_write)
+{
+ Aml *var = aml_alloc();
+ build_append_byte(var->buf, 0x86); /* Memory32Fixed Resource Descriptor */
+ build_append_byte(var->buf, 9); /* Length, bits[7:0] value = 9 */
+ build_append_byte(var->buf, 0); /* Length, bits[15:8] value = 0 */
+ build_append_byte(var->buf, read_and_write); /* Write status, 1 rw 0 ro */
+
+ /* Range base address */
+ build_append_byte(var->buf, extract32(addr, 0, 8)); /* bits[7:0] */
+ build_append_byte(var->buf, extract32(addr, 8, 8)); /* bits[15:8] */
+ build_append_byte(var->buf, extract32(addr, 16, 8)); /* bits[23:16] */
+ build_append_byte(var->buf, extract32(addr, 24, 8)); /* bits[31:24] */
+
+ /* Range length */
+ build_append_byte(var->buf, extract32(size, 0, 8)); /* bits[7:0] */
+ build_append_byte(var->buf, extract32(size, 8, 8)); /* bits[15:8] */
+ build_append_byte(var->buf, extract32(size, 16, 8)); /* bits[23:16] */
+ build_append_byte(var->buf, extract32(size, 24, 8)); /* bits[31:24] */
+ return var;
+}
+
/* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index c0e81d4..bd0d9e7 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -168,6 +168,8 @@ Aml *aml_call1(const char *method, Aml *arg1);
Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
+Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
+ AmlReadAndWrite read_and_write);
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len);
Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 06/24] hw/acpi/aml-build: Add aml_interrupt() term
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (4 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 05/24] hw/acpi/aml-build: Add aml_memory32_fixed() term Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 07/24] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
` (18 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Add aml_interrupt() for describing device interrupt in resource template.
These can be used to generating DSDT table for ACPI on ARM.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 27 +++++++++++++++++++++++++++
include/hw/acpi/aml-build.h | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 69 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index ad4d7ea..0d99941 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -533,6 +533,33 @@ Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
return var;
}
+/*
+ * ACPI 5.0: 6.4.3.6 Extended Interrupt Descriptor
+ * Type 1, Large Item Name 0x9
+ */
+Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
+ AmlLevelAndEdge level_and_edge,
+ AmlActiveHighAndLow high_and_low, AmlShared shared,
+ uint32_t irq)
+{
+ Aml *var = aml_alloc();
+ uint8_t irq_flags = con_and_pro | (level_and_edge << 1)
+ | (high_and_low << 2) | (shared << 3);
+
+ build_append_byte(var->buf, 0x89); /* Extended irq descriptor */
+ build_append_byte(var->buf, 6); /* Length, bits[7:0] minimum value = 6 */
+ build_append_byte(var->buf, 0); /* Length, bits[15:8] minimum value = 0 */
+ build_append_byte(var->buf, irq_flags); /* Interrupt Vector Information. */
+ build_append_byte(var->buf, 0x01); /* Interrupt table length = 1 */
+
+ /* Interrupt Number */
+ build_append_byte(var->buf, extract32(irq, 0, 8)); /* bits[7:0] */
+ build_append_byte(var->buf, extract32(irq, 8, 8)); /* bits[15:8] */
+ build_append_byte(var->buf, extract32(irq, 16, 8)); /* bits[23:16] */
+ build_append_byte(var->buf, extract32(irq, 24, 8)); /* bits[31:24] */
+ return var;
+}
+
/* ACPI 1.0b: 6.4.2.5 I/O Port Descriptor */
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index bd0d9e7..df23479 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -111,6 +111,44 @@ typedef enum {
AML_READ_WRITE = 1,
} AmlReadAndWrite;
+/*
+ * ACPI 5.0: Table 6-187 Extended Interrupt Descriptor Definition
+ * Interrupt Vector Flags Bits[0] Consumer/Producer
+ */
+typedef enum {
+ AML_CONSUMER_PRODUCER = 0,
+ AML_CONSUMER = 1,
+} AmlConsumerAndProducer;
+
+/*
+ * ACPI 5.0: Table 6-187 Extended Interrupt Descriptor Definition
+ * _HE field definition
+ */
+typedef enum {
+ AML_LEVEL = 0,
+ AML_EDGE = 1,
+} AmlLevelAndEdge;
+
+/*
+ * ACPI 5.0: Table 6-187 Extended Interrupt Descriptor Definition
+ * _LL field definition
+ */
+typedef enum {
+ AML_ACTIVE_HIGH = 0,
+ AML_ACTIVE_LOW = 1,
+} AmlActiveHighAndLow;
+
+/*
+ * ACPI 5.0: Table 6-187 Extended Interrupt Descriptor Definition
+ * _SHR field definition
+ */
+typedef enum {
+ AML_EXCLUSIVE = 0,
+ AML_SHARED = 1,
+ AML_EXCLUSIVE_AND_WAKE = 2,
+ AML_SHARED_AND_WAKE = 3,
+} AmlShared;
+
typedef
struct AcpiBuildTables {
GArray *table_data;
@@ -170,6 +208,10 @@ Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
AmlReadAndWrite read_and_write);
+Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
+ AmlLevelAndEdge level_and_edge,
+ AmlActiveHighAndLow high_and_low, AmlShared shared,
+ uint32_t irq);
Aml *aml_io(AmlIODecode dec, uint16_t min_base, uint16_t max_base,
uint8_t aln, uint8_t len);
Aml *aml_operation_region(const char *name, AmlRegionSpace rs,
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 07/24] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (5 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 06/24] hw/acpi/aml-build: Add aml_interrupt() term Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 08/24] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
` (17 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
DSDT consists of the usual common table header plus a definition
block in AML encoding which describes all devices in the platform.
After initializing DSDT with header information the namespace is
created which is followed by the device encodings. The devices are
described using the Resource Template for the 32-Bit Fixed Memory
Range and the Extended Interrupt Descriptors.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/arm/virt-acpi-build.c | 132 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index b8a5bd8..2cf2cc5 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -40,6 +40,134 @@
#include "hw/hw.h"
#include "hw/acpi/aml-build.h"
+#define ARM_SPI_BASE 32
+
+static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
+{
+ uint16_t i;
+
+ for (i = 0; i < smp_cpus; i++) {
+ Aml *dev = aml_device("C%03x", i);
+ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+ aml_append(scope, dev);
+ }
+}
+
+static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
+ int uart_irq)
+{
+ Aml *dev = aml_device("COM0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(uart_memmap->base,
+ uart_memmap->size, AML_READ_WRITE));
+ aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, uart_irq));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_rtc(Aml *scope, const MemMapEntry *rtc_memmap,
+ int rtc_irq)
+{
+ Aml *dev = aml_device("RTC0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0013")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(rtc_memmap->base,
+ rtc_memmap->size, AML_READ_WRITE));
+ aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, rtc_irq));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
+{
+ Aml *dev, *crs;
+ hwaddr base = flash_memmap->base;
+ hwaddr size = flash_memmap->size;
+
+ dev = aml_device("FLS0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+ crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+
+ dev = aml_device("FLS1");
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(1)));
+ crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+}
+
+static void acpi_dsdt_add_virtio(Aml *scope,
+ const MemMapEntry *virtio_mmio_memmap,
+ int mmio_irq, int num)
+{
+ hwaddr base = virtio_mmio_memmap->base;
+ hwaddr size = virtio_mmio_memmap->size;
+ int irq = mmio_irq;
+ int i;
+
+ for (i = 0; i < num; i++) {
+ Aml *dev = aml_device("VR%02u", i);
+ aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
+ aml_append(dev, aml_name_decl("_UID", aml_int(i)));
+
+ Aml *crs = aml_resource_template();
+ aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
+ aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, irq + i));
+ aml_append(dev, aml_name_decl("_CRS", crs));
+ aml_append(scope, dev);
+ base += size;
+ }
+}
+
+/* DSDT */
+static void
+build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ Aml *scope, *dsdt;
+ const MemMapEntry *memmap = guest_info->memmap;
+ const int *irqmap = guest_info->irqmap;
+
+ dsdt = init_aml_allocator();
+ /* Reserve space for header */
+ acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
+
+ scope = aml_scope("\\_SB");
+ acpi_dsdt_add_cpus(scope, guest_info->smp_cpus);
+ acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
+ (irqmap[VIRT_UART] + ARM_SPI_BASE));
+ acpi_dsdt_add_rtc(scope, &memmap[VIRT_RTC],
+ (irqmap[VIRT_RTC] + ARM_SPI_BASE));
+ acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
+ acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
+ (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
+ aml_append(dsdt, scope);
+
+ /* copy AML table into ACPI tables blob and patch header there */
+ g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
+ build_header(linker, table_data,
+ (void *)(table_data->data + table_data->len - dsdt->buf->len),
+ "DSDT", dsdt->buf->len, 5);
+ free_aml_allocator();
+}
+
typedef
struct AcpiBuildState {
/* Copy of table in RAM (for patching). */
@@ -55,6 +183,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
+ GArray *tables_blob = tables->table_data;
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
@@ -72,6 +201,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
* DSDT
*/
+ /* DSDT is pointed to by FADT */
+ build_dsdt(tables_blob, tables->linker, guest_info);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 08/24] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (6 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 07/24] hw/arm/virt-acpi-build: Generation of DSDT table for virt devices Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 8:25 ` Alex Bennée
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 09/24] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
` (16 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
In the case of mach virt, it is used to set the Hardware Reduced bit
and enable PSCI SMP booting through HVC. So ignore FACS and FADT
points to DSDT.
Update the header definitions for FADT taking into account the new
additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h`
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 31 ++++++++++
include/hw/acpi/acpi-defs.h | 135 ++++++++++++++++++++++++++++++++------------
2 files changed, 129 insertions(+), 37 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 2cf2cc5..0791501 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -137,6 +137,31 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
}
+/* FADT */
+static void
+build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
+{
+ AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
+
+ /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
+ fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
+ fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
+ (1 << ACPI_FADT_ARM_PSCI_USE_HVC));
+
+ /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
+ fadt->minor_revision = 0x1;
+
+ fadt->dsdt = cpu_to_le32(dsdt);
+ /* DSDT address to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ table_data, &fadt->dsdt,
+ sizeof fadt->dsdt);
+
+ build_header(linker, table_data,
+ (void *)fadt, "FACP", sizeof(*fadt), 5);
+}
+
/* DSDT */
static void
build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
@@ -183,6 +208,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
+ unsigned dsdt;
GArray *tables_blob = tables->table_data;
table_offsets = g_array_new(false, true /* clear */,
@@ -202,8 +228,13 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
*/
/* DSDT is pointed to by FADT */
+ dsdt = tables_blob->len;
build_dsdt(tables_blob, tables->linker, guest_info);
+ /* FADT MADT GTDT pointed to by RSDT */
+ acpi_add_table(table_offsets, tables_blob);
+ build_fadt(tables_blob, tables->linker, dsdt);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index c4468f8..fadcf84 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -88,46 +88,54 @@ struct AcpiTableHeader /* ACPI common table header */
typedef struct AcpiTableHeader AcpiTableHeader;
/*
- * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ * ACPI Fixed ACPI Description Table (FADT)
*/
+#define ACPI_FADT_COMMON_DEF /* FADT common definition */ \
+ ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
+ uint32_t firmware_ctrl; /* Physical address of FACS */ \
+ uint32_t dsdt; /* Physical address of DSDT */ \
+ uint8_t model; /* System Interrupt Model */ \
+ uint8_t reserved1; /* Reserved */ \
+ uint16_t sci_int; /* System vector of SCI interrupt */ \
+ uint32_t smi_cmd; /* Port address of SMI command port */ \
+ uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \
+ uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \
+ /* Value to write to SMI CMD to enter S4BIOS state */ \
+ uint8_t S4bios_req; \
+ uint8_t reserved2; /* Reserved - must be zero */ \
+ /* Port address of Power Mgt 1a acpi_event Reg Blk */ \
+ uint32_t pm1a_evt_blk; \
+ /* Port address of Power Mgt 1b acpi_event Reg Blk */ \
+ uint32_t pm1b_evt_blk; \
+ uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \
+ uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \
+ uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \
+ uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
+ /* Port addr of General Purpose acpi_event 0 Reg Blk */ \
+ uint32_t gpe0_blk; \
+ /* Port addr of General Purpose acpi_event 1 Reg Blk */ \
+ uint32_t gpe1_blk; \
+ uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \
+ uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \
+ uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \
+ uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \
+ uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \
+ uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \
+ uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \
+ uint8_t reserved3; /* Reserved */ \
+ uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \
+ uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \
+ uint16_t flush_size; /* Size of area read to flush caches */ \
+ uint16_t flush_stride; /* Stride used in flushing caches */ \
+ uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \
+ uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \
+ uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
+ uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
+ uint8_t century; /* Index to century in RTC CMOS RAM */
+
struct AcpiFadtDescriptorRev1
{
- ACPI_TABLE_HEADER_DEF /* ACPI common table header */
- uint32_t firmware_ctrl; /* Physical address of FACS */
- uint32_t dsdt; /* Physical address of DSDT */
- uint8_t model; /* System Interrupt Model */
- uint8_t reserved1; /* Reserved */
- uint16_t sci_int; /* System vector of SCI interrupt */
- uint32_t smi_cmd; /* Port address of SMI command port */
- uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
- uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
- uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
- uint8_t reserved2; /* Reserved - must be zero */
- uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
- uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
- uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
- uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
- uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
- uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
- uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
- uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
- uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
- uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
- uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
- uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
- uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
- uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
- uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
- uint8_t reserved3; /* Reserved */
- uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
- uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
- uint16_t flush_size; /* Size of area read to flush caches */
- uint16_t flush_stride; /* Stride used in flushing caches */
- uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
- uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
- uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
- uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
- uint8_t century; /* Index to century in RTC CMOS RAM */
+ ACPI_FADT_COMMON_DEF
uint8_t reserved4; /* Reserved */
uint8_t reserved4a; /* Reserved */
uint8_t reserved4b; /* Reserved */
@@ -135,6 +143,59 @@ struct AcpiFadtDescriptorRev1
} QEMU_PACKED;
typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
+struct AcpiGenericAddress {
+ uint8_t space_id; /* Address space where struct or register exists */
+ uint8_t bit_width; /* Size in bits of given register */
+ uint8_t bit_offset; /* Bit offset within the register */
+ uint8_t access_width; /* Minimum Access size (ACPI 3.0) */
+ uint64_t address; /* 64-bit address of struct or register */
+} QEMU_PACKED;
+
+struct AcpiFadtDescriptorRev5_1 {
+ ACPI_FADT_COMMON_DEF
+ /* IA-PC Boot Architecture Flags (see below for individual flags) */
+ uint16_t boot_flags;
+ uint8_t reserved; /* Reserved, must be zero */
+ /* Miscellaneous flag bits (see below for individual flags) */
+ uint32_t flags;
+ /* 64-bit address of the Reset register */
+ struct AcpiGenericAddress reset_register;
+ /* Value to write to the reset_register port to reset the system */
+ uint8_t reset_value;
+ /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
+ uint16_t arm_boot_flags;
+ uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */
+ uint64_t Xfacs; /* 64-bit physical address of FACS */
+ uint64_t Xdsdt; /* 64-bit physical address of DSDT */
+ /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
+ struct AcpiGenericAddress xpm1a_event_block;
+ /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
+ struct AcpiGenericAddress xpm1b_event_block;
+ /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
+ struct AcpiGenericAddress xpm1a_control_block;
+ /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
+ struct AcpiGenericAddress xpm1b_control_block;
+ /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
+ struct AcpiGenericAddress xpm2_control_block;
+ /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
+ struct AcpiGenericAddress xpm_timer_block;
+ /* 64-bit Extended General Purpose Event 0 Reg Blk address */
+ struct AcpiGenericAddress xgpe0_block;
+ /* 64-bit Extended General Purpose Event 1 Reg Blk address */
+ struct AcpiGenericAddress xgpe1_block;
+ /* 64-bit Sleep Control register (ACPI 5.0) */
+ struct AcpiGenericAddress sleep_control;
+ /* 64-bit Sleep Status register (ACPI 5.0) */
+ struct AcpiGenericAddress sleep_status;
+} QEMU_PACKED;
+
+typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
+
+enum {
+ ACPI_FADT_ARM_USE_PSCI_G_0_2 = 0,
+ ACPI_FADT_ARM_PSCI_USE_HVC = 1,
+};
+
/*
* ACPI 1.0 Root System Description Table (RSDT)
*/
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 08/24] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 08/24] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
@ 2015-05-27 8:25 ` Alex Bennée
2015-05-27 8:36 ` Shannon Zhao
0 siblings, 1 reply; 53+ messages in thread
From: Alex Bennée @ 2015-05-27 8:25 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, imammedo, pbonzini,
lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> In the case of mach virt, it is used to set the Hardware Reduced bit
> and enable PSCI SMP booting through HVC. So ignore FACS and FADT
> points to DSDT.
>
> Update the header definitions for FADT taking into account the new
> additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h`
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 31 ++++++++++
> include/hw/acpi/acpi-defs.h | 135 ++++++++++++++++++++++++++++++++------------
> 2 files changed, 129 insertions(+), 37 deletions(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 2cf2cc5..0791501 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -137,6 +137,31 @@ static void acpi_dsdt_add_virtio(Aml *scope,
> }
> }
>
> +/* FADT */
> +static void
> +build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
> +{
> + AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
> +
> + /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
> + fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
> + fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
> + (1 <<
> ACPI_FADT_ARM_PSCI_USE_HVC));
So the ACPI_FADT_* symbols are actually bit positions. Perhaps naming
them *_SHIFT will make that clearer else where.
> +
> + /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
> + fadt->minor_revision = 0x1;
> +
> + fadt->dsdt = cpu_to_le32(dsdt);
> + /* DSDT address to be filled by Guest linker */
> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
> + ACPI_BUILD_TABLE_FILE,
> + table_data, &fadt->dsdt,
> + sizeof fadt->dsdt);
> +
> + build_header(linker, table_data,
> + (void *)fadt, "FACP", sizeof(*fadt), 5);
> +}
> +
> /* DSDT */
> static void
> build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
> @@ -183,6 +208,7 @@ static
> void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> {
> GArray *table_offsets;
> + unsigned dsdt;
> GArray *tables_blob = tables->table_data;
>
> table_offsets = g_array_new(false, true /* clear */,
> @@ -202,8 +228,13 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> */
>
> /* DSDT is pointed to by FADT */
> + dsdt = tables_blob->len;
> build_dsdt(tables_blob, tables->linker, guest_info);
>
> + /* FADT MADT GTDT pointed to by RSDT */
> + acpi_add_table(table_offsets, tables_blob);
> + build_fadt(tables_blob, tables->linker, dsdt);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> index c4468f8..fadcf84 100644
> --- a/include/hw/acpi/acpi-defs.h
> +++ b/include/hw/acpi/acpi-defs.h
> @@ -88,46 +88,54 @@ struct AcpiTableHeader /* ACPI common table header */
> typedef struct AcpiTableHeader AcpiTableHeader;
>
> /*
> - * ACPI 1.0 Fixed ACPI Description Table (FADT)
> + * ACPI Fixed ACPI Description Table (FADT)
> */
> +#define ACPI_FADT_COMMON_DEF /* FADT common definition */ \
> + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
> + uint32_t firmware_ctrl; /* Physical address of FACS */ \
> + uint32_t dsdt; /* Physical address of DSDT */ \
> + uint8_t model; /* System Interrupt Model */ \
> + uint8_t reserved1; /* Reserved */ \
> + uint16_t sci_int; /* System vector of SCI interrupt */ \
> + uint32_t smi_cmd; /* Port address of SMI command port */ \
> + uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \
> + uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \
> + /* Value to write to SMI CMD to enter S4BIOS state */ \
> + uint8_t S4bios_req; \
> + uint8_t reserved2; /* Reserved - must be zero */ \
> + /* Port address of Power Mgt 1a acpi_event Reg Blk */ \
> + uint32_t pm1a_evt_blk; \
> + /* Port address of Power Mgt 1b acpi_event Reg Blk */ \
> + uint32_t pm1b_evt_blk; \
> + uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \
> + uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \
> + uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \
> + uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
> + /* Port addr of General Purpose acpi_event 0 Reg Blk */ \
> + uint32_t gpe0_blk; \
> + /* Port addr of General Purpose acpi_event 1 Reg Blk */ \
> + uint32_t gpe1_blk; \
> + uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \
> + uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \
> + uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \
> + uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \
> + uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \
> + uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \
> + uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \
> + uint8_t reserved3; /* Reserved */ \
> + uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \
> + uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \
> + uint16_t flush_size; /* Size of area read to flush caches */ \
> + uint16_t flush_stride; /* Stride used in flushing caches */ \
> + uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \
> + uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \
> + uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
> + uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
> + uint8_t century; /* Index to century in RTC CMOS RAM */
> +
> struct AcpiFadtDescriptorRev1
> {
> - ACPI_TABLE_HEADER_DEF /* ACPI common table header */
> - uint32_t firmware_ctrl; /* Physical address of FACS */
> - uint32_t dsdt; /* Physical address of DSDT */
> - uint8_t model; /* System Interrupt Model */
> - uint8_t reserved1; /* Reserved */
> - uint16_t sci_int; /* System vector of SCI interrupt */
> - uint32_t smi_cmd; /* Port address of SMI command port */
> - uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
> - uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
> - uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
> - uint8_t reserved2; /* Reserved - must be zero */
> - uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
> - uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
> - uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
> - uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
> - uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
> - uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
> - uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
> - uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
> - uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
> - uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
> - uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
> - uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
> - uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
> - uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
> - uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
> - uint8_t reserved3; /* Reserved */
> - uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
> - uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
> - uint16_t flush_size; /* Size of area read to flush caches */
> - uint16_t flush_stride; /* Stride used in flushing caches */
> - uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
> - uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
> - uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
> - uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
> - uint8_t century; /* Index to century in RTC CMOS RAM */
> + ACPI_FADT_COMMON_DEF
> uint8_t reserved4; /* Reserved */
> uint8_t reserved4a; /* Reserved */
> uint8_t reserved4b; /* Reserved */
> @@ -135,6 +143,59 @@ struct AcpiFadtDescriptorRev1
> } QEMU_PACKED;
> typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
>
> +struct AcpiGenericAddress {
> + uint8_t space_id; /* Address space where struct or register exists */
> + uint8_t bit_width; /* Size in bits of given register */
> + uint8_t bit_offset; /* Bit offset within the register */
> + uint8_t access_width; /* Minimum Access size (ACPI 3.0) */
> + uint64_t address; /* 64-bit address of struct or register */
> +} QEMU_PACKED;
> +
> +struct AcpiFadtDescriptorRev5_1 {
> + ACPI_FADT_COMMON_DEF
> + /* IA-PC Boot Architecture Flags (see below for individual flags) */
> + uint16_t boot_flags;
> + uint8_t reserved; /* Reserved, must be zero */
> + /* Miscellaneous flag bits (see below for individual flags) */
> + uint32_t flags;
> + /* 64-bit address of the Reset register */
> + struct AcpiGenericAddress reset_register;
> + /* Value to write to the reset_register port to reset the system */
> + uint8_t reset_value;
> + /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
> + uint16_t arm_boot_flags;
> + uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */
> + uint64_t Xfacs; /* 64-bit physical address of FACS */
> + uint64_t Xdsdt; /* 64-bit physical address of DSDT */
> + /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
> + struct AcpiGenericAddress xpm1a_event_block;
> + /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
> + struct AcpiGenericAddress xpm1b_event_block;
> + /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
> + struct AcpiGenericAddress xpm1a_control_block;
> + /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
> + struct AcpiGenericAddress xpm1b_control_block;
> + /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
> + struct AcpiGenericAddress xpm2_control_block;
> + /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
> + struct AcpiGenericAddress xpm_timer_block;
> + /* 64-bit Extended General Purpose Event 0 Reg Blk address */
> + struct AcpiGenericAddress xgpe0_block;
> + /* 64-bit Extended General Purpose Event 1 Reg Blk address */
> + struct AcpiGenericAddress xgpe1_block;
> + /* 64-bit Sleep Control register (ACPI 5.0) */
> + struct AcpiGenericAddress sleep_control;
> + /* 64-bit Sleep Status register (ACPI 5.0) */
> + struct AcpiGenericAddress sleep_status;
> +} QEMU_PACKED;
> +
> +typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
> +
> +enum {
> + ACPI_FADT_ARM_USE_PSCI_G_0_2 = 0,
> + ACPI_FADT_ARM_PSCI_USE_HVC = 1,
> +};
Where do these names come from? Are they really ARM specific?
I'm not sure what the benefit of the enum is here over a #define,
especially if the values mean something to the outside world. If it was
being passed around and we were doing type checking it would make more
sense.
> +
> /*
> * ACPI 1.0 Root System Description Table (RSDT)
> */
--
Alex Bennée
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 08/24] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers
2015-05-27 8:25 ` Alex Bennée
@ 2015-05-27 8:36 ` Shannon Zhao
0 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-27 8:36 UTC (permalink / raw)
To: Alex Bennée
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, imammedo, pbonzini,
lersek, christoffer.dall, shannon.zhao
On 2015/5/27 16:25, Alex Bennée wrote:
>
> Shannon Zhao <zhaoshenglong@huawei.com> writes:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> In the case of mach virt, it is used to set the Hardware Reduced bit
>> and enable PSCI SMP booting through HVC. So ignore FACS and FADT
>> points to DSDT.
>>
>> Update the header definitions for FADT taking into account the new
>> additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h`
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> ---
>> hw/arm/virt-acpi-build.c | 31 ++++++++++
>> include/hw/acpi/acpi-defs.h | 135 ++++++++++++++++++++++++++++++++------------
>> 2 files changed, 129 insertions(+), 37 deletions(-)
>>
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index 2cf2cc5..0791501 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -137,6 +137,31 @@ static void acpi_dsdt_add_virtio(Aml *scope,
>> }
>> }
>>
>> +/* FADT */
>> +static void
>> +build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
>> +{
>> + AcpiFadtDescriptorRev5_1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
>> +
>> + /* Hardware Reduced = 1 and use PSCI 0.2+ and with HVC */
>> + fadt->flags = cpu_to_le32(1 << ACPI_FADT_F_HW_REDUCED_ACPI);
>> + fadt->arm_boot_flags = cpu_to_le16((1 << ACPI_FADT_ARM_USE_PSCI_G_0_2) |
>> + (1 <<
>> ACPI_FADT_ARM_PSCI_USE_HVC));
>
> So the ACPI_FADT_* symbols are actually bit positions. Perhaps naming
> them *_SHIFT will make that clearer else where.
>
>> +
>> + /* ACPI v5.1 (fadt->revision.fadt->minor_revision) */
>> + fadt->minor_revision = 0x1;
>> +
>> + fadt->dsdt = cpu_to_le32(dsdt);
>> + /* DSDT address to be filled by Guest linker */
>> + bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
>> + ACPI_BUILD_TABLE_FILE,
>> + table_data, &fadt->dsdt,
>> + sizeof fadt->dsdt);
>> +
>> + build_header(linker, table_data,
>> + (void *)fadt, "FACP", sizeof(*fadt), 5);
>> +}
>> +
>> /* DSDT */
>> static void
>> build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
>> @@ -183,6 +208,7 @@ static
>> void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> {
>> GArray *table_offsets;
>> + unsigned dsdt;
>> GArray *tables_blob = tables->table_data;
>>
>> table_offsets = g_array_new(false, true /* clear */,
>> @@ -202,8 +228,13 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> */
>>
>> /* DSDT is pointed to by FADT */
>> + dsdt = tables_blob->len;
>> build_dsdt(tables_blob, tables->linker, guest_info);
>>
>> + /* FADT MADT GTDT pointed to by RSDT */
>> + acpi_add_table(table_offsets, tables_blob);
>> + build_fadt(tables_blob, tables->linker, dsdt);
>> +
>> /* Cleanup memory that's no longer used. */
>> g_array_free(table_offsets, true);
>> }
>> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
>> index c4468f8..fadcf84 100644
>> --- a/include/hw/acpi/acpi-defs.h
>> +++ b/include/hw/acpi/acpi-defs.h
>> @@ -88,46 +88,54 @@ struct AcpiTableHeader /* ACPI common table header */
>> typedef struct AcpiTableHeader AcpiTableHeader;
>>
>> /*
>> - * ACPI 1.0 Fixed ACPI Description Table (FADT)
>> + * ACPI Fixed ACPI Description Table (FADT)
>> */
>> +#define ACPI_FADT_COMMON_DEF /* FADT common definition */ \
>> + ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
>> + uint32_t firmware_ctrl; /* Physical address of FACS */ \
>> + uint32_t dsdt; /* Physical address of DSDT */ \
>> + uint8_t model; /* System Interrupt Model */ \
>> + uint8_t reserved1; /* Reserved */ \
>> + uint16_t sci_int; /* System vector of SCI interrupt */ \
>> + uint32_t smi_cmd; /* Port address of SMI command port */ \
>> + uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \
>> + uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \
>> + /* Value to write to SMI CMD to enter S4BIOS state */ \
>> + uint8_t S4bios_req; \
>> + uint8_t reserved2; /* Reserved - must be zero */ \
>> + /* Port address of Power Mgt 1a acpi_event Reg Blk */ \
>> + uint32_t pm1a_evt_blk; \
>> + /* Port address of Power Mgt 1b acpi_event Reg Blk */ \
>> + uint32_t pm1b_evt_blk; \
>> + uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \
>> + uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \
>> + uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \
>> + uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \
>> + /* Port addr of General Purpose acpi_event 0 Reg Blk */ \
>> + uint32_t gpe0_blk; \
>> + /* Port addr of General Purpose acpi_event 1 Reg Blk */ \
>> + uint32_t gpe1_blk; \
>> + uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \
>> + uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \
>> + uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \
>> + uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \
>> + uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \
>> + uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \
>> + uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \
>> + uint8_t reserved3; /* Reserved */ \
>> + uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \
>> + uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \
>> + uint16_t flush_size; /* Size of area read to flush caches */ \
>> + uint16_t flush_stride; /* Stride used in flushing caches */ \
>> + uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \
>> + uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \
>> + uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \
>> + uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \
>> + uint8_t century; /* Index to century in RTC CMOS RAM */
>> +
>> struct AcpiFadtDescriptorRev1
>> {
>> - ACPI_TABLE_HEADER_DEF /* ACPI common table header */
>> - uint32_t firmware_ctrl; /* Physical address of FACS */
>> - uint32_t dsdt; /* Physical address of DSDT */
>> - uint8_t model; /* System Interrupt Model */
>> - uint8_t reserved1; /* Reserved */
>> - uint16_t sci_int; /* System vector of SCI interrupt */
>> - uint32_t smi_cmd; /* Port address of SMI command port */
>> - uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
>> - uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
>> - uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
>> - uint8_t reserved2; /* Reserved - must be zero */
>> - uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
>> - uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
>> - uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
>> - uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
>> - uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
>> - uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
>> - uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
>> - uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
>> - uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
>> - uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
>> - uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
>> - uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
>> - uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
>> - uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
>> - uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
>> - uint8_t reserved3; /* Reserved */
>> - uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
>> - uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
>> - uint16_t flush_size; /* Size of area read to flush caches */
>> - uint16_t flush_stride; /* Stride used in flushing caches */
>> - uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
>> - uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
>> - uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
>> - uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
>> - uint8_t century; /* Index to century in RTC CMOS RAM */
>> + ACPI_FADT_COMMON_DEF
>> uint8_t reserved4; /* Reserved */
>> uint8_t reserved4a; /* Reserved */
>> uint8_t reserved4b; /* Reserved */
>> @@ -135,6 +143,59 @@ struct AcpiFadtDescriptorRev1
>> } QEMU_PACKED;
>> typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
>>
>> +struct AcpiGenericAddress {
>> + uint8_t space_id; /* Address space where struct or register exists */
>> + uint8_t bit_width; /* Size in bits of given register */
>> + uint8_t bit_offset; /* Bit offset within the register */
>> + uint8_t access_width; /* Minimum Access size (ACPI 3.0) */
>> + uint64_t address; /* 64-bit address of struct or register */
>> +} QEMU_PACKED;
>> +
>> +struct AcpiFadtDescriptorRev5_1 {
>> + ACPI_FADT_COMMON_DEF
>> + /* IA-PC Boot Architecture Flags (see below for individual flags) */
>> + uint16_t boot_flags;
>> + uint8_t reserved; /* Reserved, must be zero */
>> + /* Miscellaneous flag bits (see below for individual flags) */
>> + uint32_t flags;
>> + /* 64-bit address of the Reset register */
>> + struct AcpiGenericAddress reset_register;
>> + /* Value to write to the reset_register port to reset the system */
>> + uint8_t reset_value;
>> + /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */
>> + uint16_t arm_boot_flags;
>> + uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */
>> + uint64_t Xfacs; /* 64-bit physical address of FACS */
>> + uint64_t Xdsdt; /* 64-bit physical address of DSDT */
>> + /* 64-bit Extended Power Mgt 1a Event Reg Blk address */
>> + struct AcpiGenericAddress xpm1a_event_block;
>> + /* 64-bit Extended Power Mgt 1b Event Reg Blk address */
>> + struct AcpiGenericAddress xpm1b_event_block;
>> + /* 64-bit Extended Power Mgt 1a Control Reg Blk address */
>> + struct AcpiGenericAddress xpm1a_control_block;
>> + /* 64-bit Extended Power Mgt 1b Control Reg Blk address */
>> + struct AcpiGenericAddress xpm1b_control_block;
>> + /* 64-bit Extended Power Mgt 2 Control Reg Blk address */
>> + struct AcpiGenericAddress xpm2_control_block;
>> + /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */
>> + struct AcpiGenericAddress xpm_timer_block;
>> + /* 64-bit Extended General Purpose Event 0 Reg Blk address */
>> + struct AcpiGenericAddress xgpe0_block;
>> + /* 64-bit Extended General Purpose Event 1 Reg Blk address */
>> + struct AcpiGenericAddress xgpe1_block;
>> + /* 64-bit Sleep Control register (ACPI 5.0) */
>> + struct AcpiGenericAddress sleep_control;
>> + /* 64-bit Sleep Status register (ACPI 5.0) */
>> + struct AcpiGenericAddress sleep_status;
>> +} QEMU_PACKED;
>> +
>> +typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1;
>> +
>> +enum {
>> + ACPI_FADT_ARM_USE_PSCI_G_0_2 = 0,
>> + ACPI_FADT_ARM_PSCI_USE_HVC = 1,
>> +};
>
> Where do these names come from? Are they really ARM specific?
>
>From ACPI 5.1 spec:
Table 5-37 Fixed ACPI Description Table ARM Boot Architecture Flags
> I'm not sure what the benefit of the enum is here over a #define,
> especially if the values mean something to the outside world. If it was
> being passed around and we were doing type checking it would make more
> sense.
>
>> +
>> /*
>> * ACPI 1.0 Root System Description Table (RSDT)
>> */
>
--
Shannon
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 09/24] hw/arm/virt-acpi-build: Generate MADT table
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (7 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 08/24] hw/arm/virt-acpi-build: Generate FADT table and update ACPI headers Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-26 16:00 ` Igor Mammedov
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 10/24] hw/arm/virt-acpi-build: Generate GTDT table Shannon Zhao
` (15 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
MADT describes GIC enabled ARM platforms. The GICC and GICD
subtables are used to define the GIC regions.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/arm/virt-acpi-build.c | 57 ++++++++++++++++++++++++++++++++++++++++
include/hw/acpi/acpi-defs.h | 38 ++++++++++++++++++++++++++-
include/hw/arm/virt-acpi-build.h | 3 +++
3 files changed, 97 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 0791501..29ad535 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -42,6 +42,20 @@
#define ARM_SPI_BASE 32
+typedef struct VirtAcpiCpuInfo {
+ DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
+} VirtAcpiCpuInfo;
+
+static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
+{
+ CPUState *cpu;
+
+ memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
+ CPU_FOREACH(cpu) {
+ set_bit(cpu->cpu_index, cpuinfo->found_cpus);
+ }
+}
+
static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
{
uint16_t i;
@@ -137,6 +151,43 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
}
+/* MADT */
+static void
+build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
+ VirtAcpiCpuInfo *cpuinfo)
+{
+ int madt_start = table_data->len;
+ const MemMapEntry *memmap = guest_info->memmap;
+ AcpiMultipleApicTable *madt;
+ AcpiMadtGenericDistributor *gicd;
+ int i;
+
+ madt = acpi_data_push(table_data, sizeof *madt);
+
+ for (i = 0; i < guest_info->smp_cpus; i++) {
+ AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
+ sizeof *gicc);
+ gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
+ gicc->length = sizeof(*gicc);
+ gicc->base_address = memmap[VIRT_GIC_CPU].base;
+ gicc->cpu_interface_number = i;
+ gicc->arm_mpidr = i;
+ gicc->uid = i;
+ if (test_bit(i, cpuinfo->found_cpus)) {
+ gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
+ }
+ }
+
+ gicd = acpi_data_push(table_data, sizeof *gicd);
+ gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
+ gicd->length = sizeof(*gicd);
+ gicd->base_address = memmap[VIRT_GIC_DIST].base;
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + madt_start), "APIC",
+ table_data->len - madt_start, 5);
+}
+
/* FADT */
static void
build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
@@ -209,8 +260,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
unsigned dsdt;
+ VirtAcpiCpuInfo cpuinfo;
GArray *tables_blob = tables->table_data;
+ virt_acpi_get_cpu_info(&cpuinfo);
+
table_offsets = g_array_new(false, true /* clear */,
sizeof(uint32_t));
@@ -235,6 +289,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_fadt(tables_blob, tables->linker, dsdt);
+ acpi_add_table(table_offsets, tables_blob);
+ build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index fadcf84..1e9dbe7 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -256,7 +256,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
#define ACPI_APIC_IO_SAPIC 6
#define ACPI_APIC_LOCAL_SAPIC 7
#define ACPI_APIC_XRUPT_SOURCE 8
-#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
+#define ACPI_APIC_LOCAL_X2APIC 9
+#define ACPI_APIC_LOCAL_X2APIC_NMI 10
+#define ACPI_APIC_GENERIC_INTERRUPT 11
+#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
+#define ACPI_APIC_GENERIC_MSI_FRAME 13
+#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
+#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
/*
* MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
@@ -304,6 +310,36 @@ struct AcpiMadtLocalNmi {
} QEMU_PACKED;
typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
+struct AcpiMadtGenericInterrupt {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t cpu_interface_number;
+ uint32_t uid;
+ uint32_t flags;
+ uint32_t parking_version;
+ uint32_t performance_interrupt;
+ uint64_t parked_address;
+ uint64_t base_address;
+ uint64_t gicv_base_address;
+ uint64_t gich_base_address;
+ uint32_t vgic_interrupt;
+ uint64_t gicr_base_address;
+ uint64_t arm_mpidr;
+} QEMU_PACKED;
+
+typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
+
+struct AcpiMadtGenericDistributor {
+ ACPI_SUB_HEADER_DEF
+ uint16_t reserved;
+ uint32_t gic_id;
+ uint64_t base_address;
+ uint32_t global_irq_base;
+ uint32_t reserved2;
+} QEMU_PACKED;
+
+typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
+
/*
* HPET Description Table
*/
diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
index ff00121..04f174d 100644
--- a/include/hw/arm/virt-acpi-build.h
+++ b/include/hw/arm/virt-acpi-build.h
@@ -23,6 +23,9 @@
#include "qemu-common.h"
#include "hw/arm/virt.h"
+#define VIRT_ACPI_CPU_ID_LIMIT 8
+#define ACPI_GICC_ENABLED 1
+
typedef struct VirtGuestInfo {
int smp_cpus;
FWCfgState *fw_cfg;
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 09/24] hw/arm/virt-acpi-build: Generate MADT table
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 09/24] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
@ 2015-05-26 16:00 ` Igor Mammedov
2015-05-27 6:18 ` Shannon Zhao
0 siblings, 1 reply; 53+ messages in thread
From: Igor Mammedov @ 2015-05-26 16:00 UTC (permalink / raw)
To: Shannon Zhao
Cc: wei, peter.maydell, hangaohuai, Drew, mst, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, 25 May 2015 10:55:05 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> MADT describes GIC enabled ARM platforms. The GICC and GICD
> subtables are used to define the GIC regions.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> hw/arm/virt-acpi-build.c | 57 ++++++++++++++++++++++++++++++++++++++++
> include/hw/acpi/acpi-defs.h | 38 ++++++++++++++++++++++++++-
> include/hw/arm/virt-acpi-build.h | 3 +++
> 3 files changed, 97 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> index 0791501..29ad535 100644
> --- a/hw/arm/virt-acpi-build.c
> +++ b/hw/arm/virt-acpi-build.c
> @@ -42,6 +42,20 @@
>
> #define ARM_SPI_BASE 32
>
> +typedef struct VirtAcpiCpuInfo {
> + DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
> +} VirtAcpiCpuInfo;
> +
> +static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
> +{
> + CPUState *cpu;
> +
> + memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
> + CPU_FOREACH(cpu) {
> + set_bit(cpu->cpu_index, cpuinfo->found_cpus);
> + }
> +}
> +
> static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
> {
> uint16_t i;
> @@ -137,6 +151,43 @@ static void acpi_dsdt_add_virtio(Aml *scope,
> }
> }
>
> +/* MADT */
> +static void
> +build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
> + VirtAcpiCpuInfo *cpuinfo)
> +{
> + int madt_start = table_data->len;
> + const MemMapEntry *memmap = guest_info->memmap;
> + AcpiMultipleApicTable *madt;
> + AcpiMadtGenericDistributor *gicd;
> + int i;
> +
> + madt = acpi_data_push(table_data, sizeof *madt);
> +
> + for (i = 0; i < guest_info->smp_cpus; i++) {
> + AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
> + sizeof *gicc);
> + gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
> + gicc->length = sizeof(*gicc);
> + gicc->base_address = memmap[VIRT_GIC_CPU].base;
> + gicc->cpu_interface_number = i;
> + gicc->arm_mpidr = i;
this value is CPU type dependent, It would be more robust to
have CPU specific callback to return aff[0-3] values
and pack it here as described by spec.
Also virt board uses a57 and according to ARM spec MPIDR register
bits 2:7 are reserved and with smp_cpus > 4 value wouldn't follow
spec using reserved bits 2:7.
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488g/way1382037549036.html
Also looking at KVM, it has its own notion on how to encode MPIDR
packing flat vcpu_id (which is cpu_index) into affinity fields so it
won't match MPIDR in QEMU.
Perhaps we should use MPIDR as vcpu_id so that KVM wouldn't have to
reinvent it and just use QEMU supplied value or pack MPIDR into vcpu_id
the way KVM expects it.
> + gicc->uid = i;
it looks like it's upto vendor how to encode topology in affX, so if
we could avoid using aff3, i.e. limit us only to 32bit MPIDR register
I'd would rather use it for this field as well and fix DSDT to use it
also.
> + if (test_bit(i, cpuinfo->found_cpus)) {
> + gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
> + }
smp_cpus currently represents present cpus number so you
can unconditionally set ACPI_GICC_ENABLED flag.
> + }
> +
> + gicd = acpi_data_push(table_data, sizeof *gicd);
> + gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
> + gicd->length = sizeof(*gicd);
> + gicd->base_address = memmap[VIRT_GIC_DIST].base;
> +
> + build_header(linker, table_data,
> + (void *)(table_data->data + madt_start), "APIC",
> + table_data->len - madt_start, 5);
> +}
> +
> /* FADT */
> static void
> build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
> @@ -209,8 +260,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> {
> GArray *table_offsets;
> unsigned dsdt;
> + VirtAcpiCpuInfo cpuinfo;
> GArray *tables_blob = tables->table_data;
>
> + virt_acpi_get_cpu_info(&cpuinfo);
> +
> table_offsets = g_array_new(false, true /* clear */,
> sizeof(uint32_t));
>
> @@ -235,6 +289,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> acpi_add_table(table_offsets, tables_blob);
> build_fadt(tables_blob, tables->linker, dsdt);
>
> + acpi_add_table(table_offsets, tables_blob);
> + build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
> +
> /* Cleanup memory that's no longer used. */
> g_array_free(table_offsets, true);
> }
> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> index fadcf84..1e9dbe7 100644
> --- a/include/hw/acpi/acpi-defs.h
> +++ b/include/hw/acpi/acpi-defs.h
> @@ -256,7 +256,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
> #define ACPI_APIC_IO_SAPIC 6
> #define ACPI_APIC_LOCAL_SAPIC 7
> #define ACPI_APIC_XRUPT_SOURCE 8
> -#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
> +#define ACPI_APIC_LOCAL_X2APIC 9
> +#define ACPI_APIC_LOCAL_X2APIC_NMI 10
> +#define ACPI_APIC_GENERIC_INTERRUPT 11
> +#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
> +#define ACPI_APIC_GENERIC_MSI_FRAME 13
> +#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
> +#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>
> /*
> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
> @@ -304,6 +310,36 @@ struct AcpiMadtLocalNmi {
> } QEMU_PACKED;
> typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
>
> +struct AcpiMadtGenericInterrupt {
> + ACPI_SUB_HEADER_DEF
> + uint16_t reserved;
> + uint32_t cpu_interface_number;
> + uint32_t uid;
> + uint32_t flags;
> + uint32_t parking_version;
> + uint32_t performance_interrupt;
> + uint64_t parked_address;
> + uint64_t base_address;
> + uint64_t gicv_base_address;
> + uint64_t gich_base_address;
> + uint32_t vgic_interrupt;
> + uint64_t gicr_base_address;
> + uint64_t arm_mpidr;
> +} QEMU_PACKED;
> +
> +typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
> +
> +struct AcpiMadtGenericDistributor {
> + ACPI_SUB_HEADER_DEF
> + uint16_t reserved;
> + uint32_t gic_id;
> + uint64_t base_address;
> + uint32_t global_irq_base;
> + uint32_t reserved2;
> +} QEMU_PACKED;
> +
> +typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
> +
> /*
> * HPET Description Table
> */
> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
> index ff00121..04f174d 100644
> --- a/include/hw/arm/virt-acpi-build.h
> +++ b/include/hw/arm/virt-acpi-build.h
> @@ -23,6 +23,9 @@
> #include "qemu-common.h"
> #include "hw/arm/virt.h"
>
> +#define VIRT_ACPI_CPU_ID_LIMIT 8
> +#define ACPI_GICC_ENABLED 1
> +
> typedef struct VirtGuestInfo {
> int smp_cpus;
> FWCfgState *fw_cfg;
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 09/24] hw/arm/virt-acpi-build: Generate MADT table
2015-05-26 16:00 ` Igor Mammedov
@ 2015-05-27 6:18 ` Shannon Zhao
2015-05-27 9:34 ` Igor Mammedov
0 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-27 6:18 UTC (permalink / raw)
To: Igor Mammedov
Cc: wei, peter.maydell, hangaohuai, Drew, mst, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall, shannon.zhao
On 2015/5/27 0:00, Igor Mammedov wrote:
> On Mon, 25 May 2015 10:55:05 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>
>> MADT describes GIC enabled ARM platforms. The GICC and GICD
>> subtables are used to define the GIC regions.
>>
>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>> ---
>> hw/arm/virt-acpi-build.c | 57 ++++++++++++++++++++++++++++++++++++++++
>> include/hw/acpi/acpi-defs.h | 38 ++++++++++++++++++++++++++-
>> include/hw/arm/virt-acpi-build.h | 3 +++
>> 3 files changed, 97 insertions(+), 1 deletion(-)
>>
>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>> index 0791501..29ad535 100644
>> --- a/hw/arm/virt-acpi-build.c
>> +++ b/hw/arm/virt-acpi-build.c
>> @@ -42,6 +42,20 @@
>>
>> #define ARM_SPI_BASE 32
>>
>> +typedef struct VirtAcpiCpuInfo {
>> + DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
>> +} VirtAcpiCpuInfo;
>> +
>> +static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
>> +{
>> + CPUState *cpu;
>> +
>> + memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
>> + CPU_FOREACH(cpu) {
>> + set_bit(cpu->cpu_index, cpuinfo->found_cpus);
>> + }
>> +}
>> +
>> static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
>> {
>> uint16_t i;
>> @@ -137,6 +151,43 @@ static void acpi_dsdt_add_virtio(Aml *scope,
>> }
>> }
>>
>> +/* MADT */
>> +static void
>> +build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
>> + VirtAcpiCpuInfo *cpuinfo)
>> +{
>> + int madt_start = table_data->len;
>> + const MemMapEntry *memmap = guest_info->memmap;
>> + AcpiMultipleApicTable *madt;
>> + AcpiMadtGenericDistributor *gicd;
>> + int i;
>> +
>> + madt = acpi_data_push(table_data, sizeof *madt);
>> +
>> + for (i = 0; i < guest_info->smp_cpus; i++) {
>> + AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
>> + sizeof *gicc);
>> + gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
>> + gicc->length = sizeof(*gicc);
>> + gicc->base_address = memmap[VIRT_GIC_CPU].base;
>> + gicc->cpu_interface_number = i;
>> + gicc->arm_mpidr = i;
> this value is CPU type dependent, It would be more robust to
> have CPU specific callback to return aff[0-3] values
> and pack it here as described by spec.
>
> Also virt board uses a57 and according to ARM spec MPIDR register
> bits 2:7 are reserved and with smp_cpus > 4 value wouldn't follow
> spec using reserved bits 2:7.
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488g/way1382037549036.html
>
> Also looking at KVM, it has its own notion on how to encode MPIDR
> packing flat vcpu_id (which is cpu_index) into affinity fields so it
> won't match MPIDR in QEMU.
> Perhaps we should use MPIDR as vcpu_id so that KVM wouldn't have to
> reinvent it and just use QEMU supplied value or pack MPIDR into vcpu_id
> the way KVM expects it.
>
KVM limits the number of VCPUs in aff0 to 16 while a57 limits aff0 to 4
according to the spec.
On the condition that host uses a57 CPU and start a VM with >4 cpus,
according to a57 spec KVM will use the reserve bits aff0[2:7] and this
is not right. But why does KVM work well? While the ARMv8 spec does not
reserve bits of aff0[2:7], I guess kernel doesn't mask bit[2:7] since it
must be compatible for all v8 CPUs.
Since virt supports 8 vcpus now, so the MPIDR value of QEMU and KVM are
same, both are cpu_index. So I think we can stay current way. When the
GICv3 patchset goes into QEMU and virt supports more vcpus, we can use
the same way to encode MPIDR as KVM in QEMU.
>> + gicc->uid = i;
> it looks like it's upto vendor how to encode topology in affX, so if
> we could avoid using aff3, i.e. limit us only to 32bit MPIDR register
> I'd would rather use it for this field as well and fix DSDT to use it
> also.
>
>> + if (test_bit(i, cpuinfo->found_cpus)) {
>> + gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
>> + }
> smp_cpus currently represents present cpus number so you
> can unconditionally set ACPI_GICC_ENABLED flag.
>
>> + }
>> +
>> + gicd = acpi_data_push(table_data, sizeof *gicd);
>> + gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
>> + gicd->length = sizeof(*gicd);
>> + gicd->base_address = memmap[VIRT_GIC_DIST].base;
>> +
>> + build_header(linker, table_data,
>> + (void *)(table_data->data + madt_start), "APIC",
>> + table_data->len - madt_start, 5);
>> +}
>> +
>> /* FADT */
>> static void
>> build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
>> @@ -209,8 +260,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> {
>> GArray *table_offsets;
>> unsigned dsdt;
>> + VirtAcpiCpuInfo cpuinfo;
>> GArray *tables_blob = tables->table_data;
>>
>> + virt_acpi_get_cpu_info(&cpuinfo);
>> +
>> table_offsets = g_array_new(false, true /* clear */,
>> sizeof(uint32_t));
>>
>> @@ -235,6 +289,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>> acpi_add_table(table_offsets, tables_blob);
>> build_fadt(tables_blob, tables->linker, dsdt);
>>
>> + acpi_add_table(table_offsets, tables_blob);
>> + build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
>> +
>> /* Cleanup memory that's no longer used. */
>> g_array_free(table_offsets, true);
>> }
>> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
>> index fadcf84..1e9dbe7 100644
>> --- a/include/hw/acpi/acpi-defs.h
>> +++ b/include/hw/acpi/acpi-defs.h
>> @@ -256,7 +256,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
>> #define ACPI_APIC_IO_SAPIC 6
>> #define ACPI_APIC_LOCAL_SAPIC 7
>> #define ACPI_APIC_XRUPT_SOURCE 8
>> -#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
>> +#define ACPI_APIC_LOCAL_X2APIC 9
>> +#define ACPI_APIC_LOCAL_X2APIC_NMI 10
>> +#define ACPI_APIC_GENERIC_INTERRUPT 11
>> +#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
>> +#define ACPI_APIC_GENERIC_MSI_FRAME 13
>> +#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
>> +#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>>
>> /*
>> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
>> @@ -304,6 +310,36 @@ struct AcpiMadtLocalNmi {
>> } QEMU_PACKED;
>> typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
>>
>> +struct AcpiMadtGenericInterrupt {
>> + ACPI_SUB_HEADER_DEF
>> + uint16_t reserved;
>> + uint32_t cpu_interface_number;
>> + uint32_t uid;
>> + uint32_t flags;
>> + uint32_t parking_version;
>> + uint32_t performance_interrupt;
>> + uint64_t parked_address;
>> + uint64_t base_address;
>> + uint64_t gicv_base_address;
>> + uint64_t gich_base_address;
>> + uint32_t vgic_interrupt;
>> + uint64_t gicr_base_address;
>> + uint64_t arm_mpidr;
>> +} QEMU_PACKED;
>> +
>> +typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
>> +
>> +struct AcpiMadtGenericDistributor {
>> + ACPI_SUB_HEADER_DEF
>> + uint16_t reserved;
>> + uint32_t gic_id;
>> + uint64_t base_address;
>> + uint32_t global_irq_base;
>> + uint32_t reserved2;
>> +} QEMU_PACKED;
>> +
>> +typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
>> +
>> /*
>> * HPET Description Table
>> */
>> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
>> index ff00121..04f174d 100644
>> --- a/include/hw/arm/virt-acpi-build.h
>> +++ b/include/hw/arm/virt-acpi-build.h
>> @@ -23,6 +23,9 @@
>> #include "qemu-common.h"
>> #include "hw/arm/virt.h"
>>
>> +#define VIRT_ACPI_CPU_ID_LIMIT 8
>> +#define ACPI_GICC_ENABLED 1
>> +
>> typedef struct VirtGuestInfo {
>> int smp_cpus;
>> FWCfgState *fw_cfg;
>
>
> .
>
--
Shannon
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 09/24] hw/arm/virt-acpi-build: Generate MADT table
2015-05-27 6:18 ` Shannon Zhao
@ 2015-05-27 9:34 ` Igor Mammedov
2015-05-27 11:10 ` Shannon Zhao
0 siblings, 1 reply; 53+ messages in thread
From: Igor Mammedov @ 2015-05-27 9:34 UTC (permalink / raw)
To: Shannon Zhao
Cc: wei, peter.maydell, hangaohuai, Drew, mst, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall, shannon.zhao
On Wed, 27 May 2015 14:18:44 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>
> On 2015/5/27 0:00, Igor Mammedov wrote:
> > On Mon, 25 May 2015 10:55:05 +0800
> > Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> >
> >> From: Shannon Zhao <shannon.zhao@linaro.org>
> >>
> >> MADT describes GIC enabled ARM platforms. The GICC and GICD
> >> subtables are used to define the GIC regions.
> >>
> >> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> >> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> >> ---
> >> hw/arm/virt-acpi-build.c | 57 ++++++++++++++++++++++++++++++++++++++++
> >> include/hw/acpi/acpi-defs.h | 38 ++++++++++++++++++++++++++-
> >> include/hw/arm/virt-acpi-build.h | 3 +++
> >> 3 files changed, 97 insertions(+), 1 deletion(-)
> >>
> >> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
> >> index 0791501..29ad535 100644
> >> --- a/hw/arm/virt-acpi-build.c
> >> +++ b/hw/arm/virt-acpi-build.c
> >> @@ -42,6 +42,20 @@
> >>
> >> #define ARM_SPI_BASE 32
> >>
> >> +typedef struct VirtAcpiCpuInfo {
> >> + DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
> >> +} VirtAcpiCpuInfo;
> >> +
> >> +static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
> >> +{
> >> + CPUState *cpu;
> >> +
> >> + memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
> >> + CPU_FOREACH(cpu) {
> >> + set_bit(cpu->cpu_index, cpuinfo->found_cpus);
> >> + }
> >> +}
> >> +
> >> static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
> >> {
> >> uint16_t i;
> >> @@ -137,6 +151,43 @@ static void acpi_dsdt_add_virtio(Aml *scope,
> >> }
> >> }
> >>
> >> +/* MADT */
> >> +static void
> >> +build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
> >> + VirtAcpiCpuInfo *cpuinfo)
> >> +{
> >> + int madt_start = table_data->len;
> >> + const MemMapEntry *memmap = guest_info->memmap;
> >> + AcpiMultipleApicTable *madt;
> >> + AcpiMadtGenericDistributor *gicd;
> >> + int i;
> >> +
> >> + madt = acpi_data_push(table_data, sizeof *madt);
> >> +
> >> + for (i = 0; i < guest_info->smp_cpus; i++) {
> >> + AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
> >> + sizeof *gicc);
> >> + gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
> >> + gicc->length = sizeof(*gicc);
> >> + gicc->base_address = memmap[VIRT_GIC_CPU].base;
> >> + gicc->cpu_interface_number = i;
> >> + gicc->arm_mpidr = i;
> > this value is CPU type dependent, It would be more robust to
> > have CPU specific callback to return aff[0-3] values
> > and pack it here as described by spec.
> >
> > Also virt board uses a57 and according to ARM spec MPIDR register
> > bits 2:7 are reserved and with smp_cpus > 4 value wouldn't follow
> > spec using reserved bits 2:7.
> > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488g/way1382037549036.html
> >
> > Also looking at KVM, it has its own notion on how to encode MPIDR
> > packing flat vcpu_id (which is cpu_index) into affinity fields so it
> > won't match MPIDR in QEMU.
> > Perhaps we should use MPIDR as vcpu_id so that KVM wouldn't have to
> > reinvent it and just use QEMU supplied value or pack MPIDR into vcpu_id
> > the way KVM expects it.
> >
>
> KVM limits the number of VCPUs in aff0 to 16 while a57 limits aff0 to 4
> according to the spec.
> On the condition that host uses a57 CPU and start a VM with >4 cpus,
> according to a57 spec KVM will use the reserve bits aff0[2:7] and this
> is not right. But why does KVM work well? While the ARMv8 spec does not
> reserve bits of aff0[2:7], I guess kernel doesn't mask bit[2:7] since it
> must be compatible for all v8 CPUs.
>
> Since virt supports 8 vcpus now, so the MPIDR value of QEMU and KVM are
> same, both are cpu_index. So I think we can stay current way. When the
> GICv3 patchset goes into QEMU and virt supports more vcpus, we can use
> the same way to encode MPIDR as KVM in QEMU.
It's bound to break once CPU count goes over 16 and it's better to adhere
CPU spec in regards to mipdr while we don't have a legacy stuff to support yet.
Yes, it's CPU type depended but that's one more reason to let QEMU deal
with its encoding and force KVM to use QEMU supplied mpidr rather than
reinventing its own interpretation of it.
In addition if we look at base a53 spec where aff0 is [0:7] bits wide,
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500f/BEIEGIGI.html
it says that valid values for aff0 is 0-3, i.e. actually using only [0:1] bits
All that said its not the reason to block this series over mpidr
re-factoring, but it would be better to use here CPU provided affX values
and encode them as per ACPI spec, then we won't have to redo this part
of code in the future.
As for UID value we can pack all aff[0-3] values inside 32 UID since
each is 8 bits wide max.
>
> >> + gicc->uid = i;
> > it looks like it's upto vendor how to encode topology in affX, so if
> > we could avoid using aff3, i.e. limit us only to 32bit MPIDR register
> > I'd would rather use it for this field as well and fix DSDT to use it
> > also.
> >
> >> + if (test_bit(i, cpuinfo->found_cpus)) {
> >> + gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
> >> + }
> > smp_cpus currently represents present cpus number so you
> > can unconditionally set ACPI_GICC_ENABLED flag.
> >
> >> + }
> >> +
> >> + gicd = acpi_data_push(table_data, sizeof *gicd);
> >> + gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
> >> + gicd->length = sizeof(*gicd);
> >> + gicd->base_address = memmap[VIRT_GIC_DIST].base;
> >> +
> >> + build_header(linker, table_data,
> >> + (void *)(table_data->data + madt_start), "APIC",
> >> + table_data->len - madt_start, 5);
> >> +}
> >> +
> >> /* FADT */
> >> static void
> >> build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
> >> @@ -209,8 +260,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> >> {
> >> GArray *table_offsets;
> >> unsigned dsdt;
> >> + VirtAcpiCpuInfo cpuinfo;
> >> GArray *tables_blob = tables->table_data;
> >>
> >> + virt_acpi_get_cpu_info(&cpuinfo);
> >> +
> >> table_offsets = g_array_new(false, true /* clear */,
> >> sizeof(uint32_t));
> >>
> >> @@ -235,6 +289,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
> >> acpi_add_table(table_offsets, tables_blob);
> >> build_fadt(tables_blob, tables->linker, dsdt);
> >>
> >> + acpi_add_table(table_offsets, tables_blob);
> >> + build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
> >> +
> >> /* Cleanup memory that's no longer used. */
> >> g_array_free(table_offsets, true);
> >> }
> >> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
> >> index fadcf84..1e9dbe7 100644
> >> --- a/include/hw/acpi/acpi-defs.h
> >> +++ b/include/hw/acpi/acpi-defs.h
> >> @@ -256,7 +256,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
> >> #define ACPI_APIC_IO_SAPIC 6
> >> #define ACPI_APIC_LOCAL_SAPIC 7
> >> #define ACPI_APIC_XRUPT_SOURCE 8
> >> -#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
> >> +#define ACPI_APIC_LOCAL_X2APIC 9
> >> +#define ACPI_APIC_LOCAL_X2APIC_NMI 10
> >> +#define ACPI_APIC_GENERIC_INTERRUPT 11
> >> +#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
> >> +#define ACPI_APIC_GENERIC_MSI_FRAME 13
> >> +#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
> >> +#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
> >>
> >> /*
> >> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
> >> @@ -304,6 +310,36 @@ struct AcpiMadtLocalNmi {
> >> } QEMU_PACKED;
> >> typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
> >>
> >> +struct AcpiMadtGenericInterrupt {
> >> + ACPI_SUB_HEADER_DEF
> >> + uint16_t reserved;
> >> + uint32_t cpu_interface_number;
> >> + uint32_t uid;
> >> + uint32_t flags;
> >> + uint32_t parking_version;
> >> + uint32_t performance_interrupt;
> >> + uint64_t parked_address;
> >> + uint64_t base_address;
> >> + uint64_t gicv_base_address;
> >> + uint64_t gich_base_address;
> >> + uint32_t vgic_interrupt;
> >> + uint64_t gicr_base_address;
> >> + uint64_t arm_mpidr;
> >> +} QEMU_PACKED;
> >> +
> >> +typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
> >> +
> >> +struct AcpiMadtGenericDistributor {
> >> + ACPI_SUB_HEADER_DEF
> >> + uint16_t reserved;
> >> + uint32_t gic_id;
> >> + uint64_t base_address;
> >> + uint32_t global_irq_base;
> >> + uint32_t reserved2;
> >> +} QEMU_PACKED;
> >> +
> >> +typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
> >> +
> >> /*
> >> * HPET Description Table
> >> */
> >> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
> >> index ff00121..04f174d 100644
> >> --- a/include/hw/arm/virt-acpi-build.h
> >> +++ b/include/hw/arm/virt-acpi-build.h
> >> @@ -23,6 +23,9 @@
> >> #include "qemu-common.h"
> >> #include "hw/arm/virt.h"
> >>
> >> +#define VIRT_ACPI_CPU_ID_LIMIT 8
> >> +#define ACPI_GICC_ENABLED 1
> >> +
> >> typedef struct VirtGuestInfo {
> >> int smp_cpus;
> >> FWCfgState *fw_cfg;
> >
> >
> > .
> >
>
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 09/24] hw/arm/virt-acpi-build: Generate MADT table
2015-05-27 9:34 ` Igor Mammedov
@ 2015-05-27 11:10 ` Shannon Zhao
0 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-27 11:10 UTC (permalink / raw)
To: Igor Mammedov, Shannon Zhao
Cc: wei, peter.maydell, hangaohuai, Drew, mst, a.spyridakis,
claudio.fontana, qemu-devel, peter.huangpeng, alex.bennee,
hanjun.guo, pbonzini, lersek, christoffer.dall
On 2015/5/27 17:34, Igor Mammedov wrote:
> On Wed, 27 May 2015 14:18:44 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
>>
>>
>> On 2015/5/27 0:00, Igor Mammedov wrote:
>>> On Mon, 25 May 2015 10:55:05 +0800
>>> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>>>
>>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>>
>>>> MADT describes GIC enabled ARM platforms. The GICC and GICD
>>>> subtables are used to define the GIC regions.
>>>>
>>>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>>> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
>>>> ---
>>>> hw/arm/virt-acpi-build.c | 57 ++++++++++++++++++++++++++++++++++++++++
>>>> include/hw/acpi/acpi-defs.h | 38 ++++++++++++++++++++++++++-
>>>> include/hw/arm/virt-acpi-build.h | 3 +++
>>>> 3 files changed, 97 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
>>>> index 0791501..29ad535 100644
>>>> --- a/hw/arm/virt-acpi-build.c
>>>> +++ b/hw/arm/virt-acpi-build.c
>>>> @@ -42,6 +42,20 @@
>>>>
>>>> #define ARM_SPI_BASE 32
>>>>
>>>> +typedef struct VirtAcpiCpuInfo {
>>>> + DECLARE_BITMAP(found_cpus, VIRT_ACPI_CPU_ID_LIMIT);
>>>> +} VirtAcpiCpuInfo;
>>>> +
>>>> +static void virt_acpi_get_cpu_info(VirtAcpiCpuInfo *cpuinfo)
>>>> +{
>>>> + CPUState *cpu;
>>>> +
>>>> + memset(cpuinfo->found_cpus, 0, sizeof cpuinfo->found_cpus);
>>>> + CPU_FOREACH(cpu) {
>>>> + set_bit(cpu->cpu_index, cpuinfo->found_cpus);
>>>> + }
>>>> +}
>>>> +
>>>> static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus)
>>>> {
>>>> uint16_t i;
>>>> @@ -137,6 +151,43 @@ static void acpi_dsdt_add_virtio(Aml *scope,
>>>> }
>>>> }
>>>>
>>>> +/* MADT */
>>>> +static void
>>>> +build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
>>>> + VirtAcpiCpuInfo *cpuinfo)
>>>> +{
>>>> + int madt_start = table_data->len;
>>>> + const MemMapEntry *memmap = guest_info->memmap;
>>>> + AcpiMultipleApicTable *madt;
>>>> + AcpiMadtGenericDistributor *gicd;
>>>> + int i;
>>>> +
>>>> + madt = acpi_data_push(table_data, sizeof *madt);
>>>> +
>>>> + for (i = 0; i < guest_info->smp_cpus; i++) {
>>>> + AcpiMadtGenericInterrupt *gicc = acpi_data_push(table_data,
>>>> + sizeof *gicc);
>>>> + gicc->type = ACPI_APIC_GENERIC_INTERRUPT;
>>>> + gicc->length = sizeof(*gicc);
>>>> + gicc->base_address = memmap[VIRT_GIC_CPU].base;
>>>> + gicc->cpu_interface_number = i;
>>>> + gicc->arm_mpidr = i;
>>> this value is CPU type dependent, It would be more robust to
>>> have CPU specific callback to return aff[0-3] values
>>> and pack it here as described by spec.
>>>
>>> Also virt board uses a57 and according to ARM spec MPIDR register
>>> bits 2:7 are reserved and with smp_cpus > 4 value wouldn't follow
>>> spec using reserved bits 2:7.
>>> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488g/way1382037549036.html
>>>
>>> Also looking at KVM, it has its own notion on how to encode MPIDR
>>> packing flat vcpu_id (which is cpu_index) into affinity fields so it
>>> won't match MPIDR in QEMU.
>>> Perhaps we should use MPIDR as vcpu_id so that KVM wouldn't have to
>>> reinvent it and just use QEMU supplied value or pack MPIDR into vcpu_id
>>> the way KVM expects it.
>>>
>>
>> KVM limits the number of VCPUs in aff0 to 16 while a57 limits aff0 to 4
>> according to the spec.
>> On the condition that host uses a57 CPU and start a VM with >4 cpus,
>> according to a57 spec KVM will use the reserve bits aff0[2:7] and this
>> is not right. But why does KVM work well? While the ARMv8 spec does not
>> reserve bits of aff0[2:7], I guess kernel doesn't mask bit[2:7] since it
>> must be compatible for all v8 CPUs.
>>
>> Since virt supports 8 vcpus now, so the MPIDR value of QEMU and KVM are
>> same, both are cpu_index. So I think we can stay current way. When the
>> GICv3 patchset goes into QEMU and virt supports more vcpus, we can use
>> the same way to encode MPIDR as KVM in QEMU.
> It's bound to break once CPU count goes over 16 and it's better to adhere
> CPU spec in regards to mipdr while we don't have a legacy stuff to support yet.
> Yes, it's CPU type depended but that's one more reason to let QEMU deal
> with its encoding and force KVM to use QEMU supplied mpidr rather than
> reinventing its own interpretation of it.
> In addition if we look at base a53 spec where aff0 is [0:7] bits wide,
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500f/BEIEGIGI.html
> it says that valid values for aff0 is 0-3, i.e. actually using only [0:1] bits
>
And from Shlomo's patchset [1] which adds GICv3 support in QEMU I know
that GIC-500 supports 8 cpus per cluster and he encodes mpidr like below:
+ aff0 = cpuid % 8;
+ aff1 = cpuid / 8;
+ mpidr = (aff1 << 8) | aff0;
[1] [PATCH RFC V2 0/4] Implement GIC-500 from GICv3 family for arm64
So there are so many different ways to encode mpidr and every one has
its reason. KVM does that as GICv3 can be able to address each CPU
directly when sending IPIs, Shlomo refers to the GIC-500 spec and here
we want to be consistent with A57 and A53 spec.
> All that said its not the reason to block this series over mpidr
> re-factoring,
Yes, it should not block this series.
> but it would be better to use here CPU provided affX values
> and encode them as per ACPI spec, then we won't have to redo this part
> of code in the future.
>
When adding GICv3 support, we have to touch these code in the future. At
that moment or after this series, we could discuss how to encode mpidr
both in QEMU and KVM.
> As for UID value we can pack all aff[0-3] values inside 32 UID since
> each is 8 bits wide max.
>
Will aff3 be used? If it's used, there are at least 4*256*256*1 VCPUs.
>>
>>>> + gicc->uid = i;
>>> it looks like it's upto vendor how to encode topology in affX, so if
>>> we could avoid using aff3, i.e. limit us only to 32bit MPIDR register
>>> I'd would rather use it for this field as well and fix DSDT to use it
>>> also.
>>>
>>>> + if (test_bit(i, cpuinfo->found_cpus)) {
>>>> + gicc->flags = cpu_to_le32(ACPI_GICC_ENABLED);
>>>> + }
>>> smp_cpus currently represents present cpus number so you
>>> can unconditionally set ACPI_GICC_ENABLED flag.
>>>
>>>> + }
>>>> +
>>>> + gicd = acpi_data_push(table_data, sizeof *gicd);
>>>> + gicd->type = ACPI_APIC_GENERIC_DISTRIBUTOR;
>>>> + gicd->length = sizeof(*gicd);
>>>> + gicd->base_address = memmap[VIRT_GIC_DIST].base;
>>>> +
>>>> + build_header(linker, table_data,
>>>> + (void *)(table_data->data + madt_start), "APIC",
>>>> + table_data->len - madt_start, 5);
>>>> +}
>>>> +
>>>> /* FADT */
>>>> static void
>>>> build_fadt(GArray *table_data, GArray *linker, unsigned dsdt)
>>>> @@ -209,8 +260,11 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>>>> {
>>>> GArray *table_offsets;
>>>> unsigned dsdt;
>>>> + VirtAcpiCpuInfo cpuinfo;
>>>> GArray *tables_blob = tables->table_data;
>>>>
>>>> + virt_acpi_get_cpu_info(&cpuinfo);
>>>> +
>>>> table_offsets = g_array_new(false, true /* clear */,
>>>> sizeof(uint32_t));
>>>>
>>>> @@ -235,6 +289,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
>>>> acpi_add_table(table_offsets, tables_blob);
>>>> build_fadt(tables_blob, tables->linker, dsdt);
>>>>
>>>> + acpi_add_table(table_offsets, tables_blob);
>>>> + build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
>>>> +
>>>> /* Cleanup memory that's no longer used. */
>>>> g_array_free(table_offsets, true);
>>>> }
>>>> diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
>>>> index fadcf84..1e9dbe7 100644
>>>> --- a/include/hw/acpi/acpi-defs.h
>>>> +++ b/include/hw/acpi/acpi-defs.h
>>>> @@ -256,7 +256,13 @@ typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
>>>> #define ACPI_APIC_IO_SAPIC 6
>>>> #define ACPI_APIC_LOCAL_SAPIC 7
>>>> #define ACPI_APIC_XRUPT_SOURCE 8
>>>> -#define ACPI_APIC_RESERVED 9 /* 9 and greater are reserved */
>>>> +#define ACPI_APIC_LOCAL_X2APIC 9
>>>> +#define ACPI_APIC_LOCAL_X2APIC_NMI 10
>>>> +#define ACPI_APIC_GENERIC_INTERRUPT 11
>>>> +#define ACPI_APIC_GENERIC_DISTRIBUTOR 12
>>>> +#define ACPI_APIC_GENERIC_MSI_FRAME 13
>>>> +#define ACPI_APIC_GENERIC_REDISTRIBUTOR 14
>>>> +#define ACPI_APIC_RESERVED 15 /* 15 and greater are reserved */
>>>>
>>>> /*
>>>> * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
>>>> @@ -304,6 +310,36 @@ struct AcpiMadtLocalNmi {
>>>> } QEMU_PACKED;
>>>> typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
>>>>
>>>> +struct AcpiMadtGenericInterrupt {
>>>> + ACPI_SUB_HEADER_DEF
>>>> + uint16_t reserved;
>>>> + uint32_t cpu_interface_number;
>>>> + uint32_t uid;
>>>> + uint32_t flags;
>>>> + uint32_t parking_version;
>>>> + uint32_t performance_interrupt;
>>>> + uint64_t parked_address;
>>>> + uint64_t base_address;
>>>> + uint64_t gicv_base_address;
>>>> + uint64_t gich_base_address;
>>>> + uint32_t vgic_interrupt;
>>>> + uint64_t gicr_base_address;
>>>> + uint64_t arm_mpidr;
>>>> +} QEMU_PACKED;
>>>> +
>>>> +typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt;
>>>> +
>>>> +struct AcpiMadtGenericDistributor {
>>>> + ACPI_SUB_HEADER_DEF
>>>> + uint16_t reserved;
>>>> + uint32_t gic_id;
>>>> + uint64_t base_address;
>>>> + uint32_t global_irq_base;
>>>> + uint32_t reserved2;
>>>> +} QEMU_PACKED;
>>>> +
>>>> +typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
>>>> +
>>>> /*
>>>> * HPET Description Table
>>>> */
>>>> diff --git a/include/hw/arm/virt-acpi-build.h b/include/hw/arm/virt-acpi-build.h
>>>> index ff00121..04f174d 100644
>>>> --- a/include/hw/arm/virt-acpi-build.h
>>>> +++ b/include/hw/arm/virt-acpi-build.h
>>>> @@ -23,6 +23,9 @@
>>>> #include "qemu-common.h"
>>>> #include "hw/arm/virt.h"
>>>>
>>>> +#define VIRT_ACPI_CPU_ID_LIMIT 8
>>>> +#define ACPI_GICC_ENABLED 1
>>>> +
>>>> typedef struct VirtGuestInfo {
>>>> int smp_cpus;
>>>> FWCfgState *fw_cfg;
>>>
>>>
>>> .
>>>
>>
>
--
Shannon
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 10/24] hw/arm/virt-acpi-build: Generate GTDT table
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (8 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 09/24] hw/arm/virt-acpi-build: Generate MADT table Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 11/24] hw/arm/virt-acpi-build: Generate RSDT table Shannon Zhao
` (14 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer
related information in the system. The Arch Timer interrupts must
be provided for GTDT.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/arm/virt-acpi-build.c | 29 +++++++++++++++++++++++++++++
hw/arm/virt.c | 8 ++++----
include/hw/acpi/acpi-defs.h | 37 +++++++++++++++++++++++++++++++++++++
include/hw/arm/virt.h | 5 +++++
4 files changed, 75 insertions(+), 4 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 29ad535..90587ad 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -151,6 +151,32 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
}
+/* GTDT */
+static void
+build_gtdt(GArray *table_data, GArray *linker)
+{
+ int gtdt_start = table_data->len;
+ AcpiGenericTimerTable *gtdt;
+
+ gtdt = acpi_data_push(table_data, sizeof *gtdt);
+ /* The interrupt values are the same with the device tree when adding 16 */
+ gtdt->secure_el1_interrupt = ARCH_TIMER_S_EL1_IRQ + 16;
+ gtdt->secure_el1_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->non_secure_el1_interrupt = ARCH_TIMER_NS_EL1_IRQ + 16;
+ gtdt->non_secure_el1_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->virtual_timer_interrupt = ARCH_TIMER_VIRT_IRQ + 16;
+ gtdt->virtual_timer_flags = ACPI_EDGE_SENSITIVE;
+
+ gtdt->non_secure_el2_interrupt = ARCH_TIMER_NS_EL2_IRQ + 16;
+ gtdt->non_secure_el2_flags = ACPI_EDGE_SENSITIVE;
+
+ build_header(linker, table_data,
+ (void *)(table_data->data + gtdt_start), "GTDT",
+ table_data->len - gtdt_start, 5);
+}
+
/* MADT */
static void
build_madt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info,
@@ -292,6 +318,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_madt(tables_blob, tables->linker, guest_info, &cpuinfo);
+ acpi_add_table(table_offsets, tables_blob);
+ build_gtdt(tables_blob, tables->linker);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 250b9bc..a6a399d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -265,10 +265,10 @@ static void fdt_add_timer_nodes(const VirtBoardInfo *vbi)
"arm,armv7-timer");
}
qemu_fdt_setprop_cells(vbi->fdt, "/timer", "interrupts",
- GIC_FDT_IRQ_TYPE_PPI, 13, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 14, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 11, irqflags,
- GIC_FDT_IRQ_TYPE_PPI, 10, irqflags);
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
}
static void fdt_add_cpu_nodes(const VirtBoardInfo *vbi)
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
index 1e9dbe7..f503ec4 100644
--- a/include/hw/acpi/acpi-defs.h
+++ b/include/hw/acpi/acpi-defs.h
@@ -341,6 +341,43 @@ struct AcpiMadtGenericDistributor {
typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor;
/*
+ * Generic Timer Description Table (GTDT)
+ */
+
+#define ACPI_GTDT_INTERRUPT_MODE (1 << 0)
+#define ACPI_GTDT_INTERRUPT_POLARITY (1 << 1)
+#define ACPI_GTDT_ALWAYS_ON (1 << 2)
+
+/* Triggering */
+
+#define ACPI_LEVEL_SENSITIVE ((uint8_t) 0x00)
+#define ACPI_EDGE_SENSITIVE ((uint8_t) 0x01)
+
+/* Polarity */
+
+#define ACPI_ACTIVE_HIGH ((uint8_t) 0x00)
+#define ACPI_ACTIVE_LOW ((uint8_t) 0x01)
+#define ACPI_ACTIVE_BOTH ((uint8_t) 0x02)
+
+struct AcpiGenericTimerTable {
+ ACPI_TABLE_HEADER_DEF
+ uint64_t counter_block_addresss;
+ uint32_t reserved;
+ uint32_t secure_el1_interrupt;
+ uint32_t secure_el1_flags;
+ uint32_t non_secure_el1_interrupt;
+ uint32_t non_secure_el1_flags;
+ uint32_t virtual_timer_interrupt;
+ uint32_t virtual_timer_flags;
+ uint32_t non_secure_el2_interrupt;
+ uint32_t non_secure_el2_flags;
+ uint64_t counter_read_block_address;
+ uint32_t platform_timer_count;
+ uint32_t platform_timer_offset;
+} QEMU_PACKED;
+typedef struct AcpiGenericTimerTable AcpiGenericTimerTable;
+
+/*
* HPET Description Table
*/
struct Acpi20Hpet {
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 49a85cc..ceec8b3 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -34,6 +34,11 @@
#define NUM_VIRTIO_TRANSPORTS 32
+#define ARCH_TIMER_VIRT_IRQ 11
+#define ARCH_TIMER_S_EL1_IRQ 13
+#define ARCH_TIMER_NS_EL1_IRQ 14
+#define ARCH_TIMER_NS_EL2_IRQ 10
+
enum {
VIRT_FLASH,
VIRT_MEM,
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 11/24] hw/arm/virt-acpi-build: Generate RSDT table
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (9 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 10/24] hw/arm/virt-acpi-build: Generate GTDT table Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 12/24] hw/arm/virt-acpi-build: Generate RSDP table Shannon Zhao
` (13 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86.
Here we still use RSDT as UEFI puts ACPI tables below 4G address space,
and UEFI ignore the RSDT or XSDT.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/acpi/aml-build.c | 24 ++++++++++++++++++++++++
hw/arm/virt-acpi-build.c | 3 +++
hw/i386/acpi-build.c | 24 ------------------------
include/hw/acpi/aml-build.h | 2 ++
4 files changed, 29 insertions(+), 24 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 0d99941..de19c63 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1006,3 +1006,27 @@ void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
g_array_free(tables->table_data, true);
g_array_free(tables->tcpalog, mfre);
}
+
+/* Build rsdt table */
+void
+build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
+{
+ AcpiRsdtDescriptorRev1 *rsdt;
+ size_t rsdt_len;
+ int i;
+ const int table_data_len = (sizeof(uint32_t) * table_offsets->len);
+
+ rsdt_len = sizeof(*rsdt) + table_data_len;
+ rsdt = acpi_data_push(table_data, rsdt_len);
+ memcpy(rsdt->table_offset_entry, table_offsets->data, table_data_len);
+ for (i = 0; i < table_offsets->len; ++i) {
+ /* rsdt->table_offset_entry to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker,
+ ACPI_BUILD_TABLE_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ table_data, &rsdt->table_offset_entry[i],
+ sizeof(uint32_t));
+ }
+ build_header(linker, table_data,
+ (void *)rsdt, "RSDT", rsdt_len, 1);
+}
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 90587ad..95c84d6 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -321,6 +321,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_gtdt(tables_blob, tables->linker);
+ /* RSDT is pointed to by RSDP */
+ build_rsdt(tables_blob, tables->linker, table_offsets);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index c7c6b61..3d19de6 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1208,30 +1208,6 @@ build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
misc->dsdt_size, 1);
}
-/* Build final rsdt table */
-static void
-build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
-{
- AcpiRsdtDescriptorRev1 *rsdt;
- size_t rsdt_len;
- int i;
-
- rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
- rsdt = acpi_data_push(table_data, rsdt_len);
- memcpy(rsdt->table_offset_entry, table_offsets->data,
- sizeof(uint32_t) * table_offsets->len);
- for (i = 0; i < table_offsets->len; ++i) {
- /* rsdt->table_offset_entry to be filled by Guest linker */
- bios_linker_loader_add_pointer(linker,
- ACPI_BUILD_TABLE_FILE,
- ACPI_BUILD_TABLE_FILE,
- table_data, &rsdt->table_offset_entry[i],
- sizeof(uint32_t));
- }
- build_header(linker, table_data,
- (void *)rsdt, "RSDT", rsdt_len, 1);
-}
-
static GArray *
build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index df23479..f4e678f 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -266,5 +266,7 @@ unsigned acpi_data_len(GArray *table);
void acpi_add_table(GArray *table_offsets, GArray *table_data);
void acpi_build_tables_init(AcpiBuildTables *tables);
void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre);
+void
+build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets);
#endif
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 12/24] hw/arm/virt-acpi-build: Generate RSDP table
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (10 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 11/24] hw/arm/virt-acpi-build: Generate RSDT table Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 13/24] hw/arm/virt-acpi-build: Generate MCFG table Shannon Zhao
` (12 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
RSDP points to RSDT which in turn points to other tables.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/arm/virt-acpi-build.c | 35 ++++++++++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 95c84d6..f8c1dd8 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -151,6 +151,35 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
}
+/* RSDP */
+static GArray *
+build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
+{
+ AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
+
+ bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
+ true /* fseg memory */);
+
+ memcpy(&rsdp->signature, "RSD PTR ", sizeof(rsdp->signature));
+ memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, sizeof(rsdp->oem_id));
+ rsdp->length = cpu_to_le32(sizeof(*rsdp));
+ rsdp->revision = 0x02;
+
+ /* Point to RSDT */
+ rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
+ /* Address to be filled by Guest linker */
+ bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
+ ACPI_BUILD_TABLE_FILE,
+ rsdp_table, &rsdp->rsdt_physical_address,
+ sizeof rsdp->rsdt_physical_address);
+ rsdp->checksum = 0;
+ /* Checksum to be filled by Guest linker */
+ bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
+ rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
+
+ return rsdp_table;
+}
+
/* GTDT */
static void
build_gtdt(GArray *table_data, GArray *linker)
@@ -285,7 +314,7 @@ static
void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
{
GArray *table_offsets;
- unsigned dsdt;
+ unsigned dsdt, rsdt;
VirtAcpiCpuInfo cpuinfo;
GArray *tables_blob = tables->table_data;
@@ -322,8 +351,12 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
build_gtdt(tables_blob, tables->linker);
/* RSDT is pointed to by RSDP */
+ rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets);
+ /* RSDP is in FSEG memory, so allocate it separately */
+ build_rsdp(tables->rsdp, tables->linker, rsdt);
+
/* Cleanup memory that's no longer used. */
g_array_free(table_offsets, true);
}
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 13/24] hw/arm/virt-acpi-build: Generate MCFG table
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (11 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 12/24] hw/arm/virt-acpi-build: Generate RSDP table Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 14/24] hw/acpi/aml-build: Make aml_buffer() definition consistent with the spec Shannon Zhao
` (11 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Generate MCFG table for PCIe controller.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
---
hw/arm/virt-acpi-build.c | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index f8c1dd8..95c83ee 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -39,6 +39,7 @@
#include "hw/loader.h"
#include "hw/hw.h"
#include "hw/acpi/aml-build.h"
+#include "hw/pci/pcie_host.h"
#define ARM_SPI_BASE 32
@@ -180,6 +181,25 @@ build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
return rsdp_table;
}
+static void
+build_mcfg(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
+{
+ AcpiTableMcfg *mcfg;
+ const MemMapEntry *memmap = guest_info->memmap;
+ int len = sizeof(*mcfg) + sizeof(mcfg->allocation[0]);
+
+ mcfg = acpi_data_push(table_data, len);
+ mcfg->allocation[0].address = cpu_to_le64(memmap[VIRT_PCIE_ECAM].base);
+
+ /* Only a single allocation so no need to play with segments */
+ mcfg->allocation[0].pci_segment = cpu_to_le16(0);
+ mcfg->allocation[0].start_bus_number = 0;
+ mcfg->allocation[0].end_bus_number = (memmap[VIRT_PCIE_ECAM].size
+ / PCIE_MMCFG_SIZE_MIN) - 1;
+
+ build_header(linker, table_data, (void *)mcfg, "MCFG", len, 5);
+}
+
/* GTDT */
static void
build_gtdt(GArray *table_data, GArray *linker)
@@ -350,6 +370,9 @@ void virt_acpi_build(VirtGuestInfo *guest_info, AcpiBuildTables *tables)
acpi_add_table(table_offsets, tables_blob);
build_gtdt(tables_blob, tables->linker);
+ acpi_add_table(table_offsets, tables_blob);
+ build_mcfg(tables_blob, tables->linker, guest_info);
+
/* RSDT is pointed to by RSDP */
rsdt = tables_blob->len;
build_rsdt(tables_blob, tables->linker, table_offsets);
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 14/24] hw/acpi/aml-build: Make aml_buffer() definition consistent with the spec
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (12 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 13/24] hw/arm/virt-acpi-build: Generate MCFG table Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 10:09 ` Michael S. Tsirkin
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 15/24] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
` (10 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
According to ACPI spec, DefBuffer can take two parameters: BufferSize
and ByteList. Make it consistent with the spec. Uninitialized buffer
could be requested by passing ByteList as NULL to reserve space.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 16 ++++++++++++++--
include/hw/acpi/aml-build.h | 2 +-
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index de19c63..22478c2 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -642,10 +642,22 @@ Aml *aml_resource_template(void)
return var;
}
-/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
-Aml *aml_buffer(void)
+/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer
+ * Pass byte_list as NULL to request uninitialized buffer to reserve space.
+ */
+Aml *aml_buffer(int buffer_size, uint8_t *byte_list)
{
+ int i;
Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
+
+ for (i = 0; i < buffer_size; i++) {
+ if (byte_list == NULL) {
+ build_append_byte(var->buf, 0x0);
+ } else {
+ build_append_byte(var->buf, byte_list[i]);
+ }
+ }
+
return var;
}
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index f4e678f..fac70ea 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -253,7 +253,7 @@ Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_method(const char *name, int arg_count);
Aml *aml_if(Aml *predicate);
Aml *aml_package(uint8_t num_elements);
-Aml *aml_buffer(void);
+Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
Aml *aml_varpackage(uint32_t num_elements);
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 14/24] hw/acpi/aml-build: Make aml_buffer() definition consistent with the spec
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 14/24] hw/acpi/aml-build: Make aml_buffer() definition consistent with the spec Shannon Zhao
@ 2015-05-27 10:09 ` Michael S. Tsirkin
0 siblings, 0 replies; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:09 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, May 25, 2015 at 10:55:10AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> According to ACPI spec, DefBuffer can take two parameters: BufferSize
> and ByteList. Make it consistent with the spec. Uninitialized buffer
> could be requested by passing ByteList as NULL to reserve space.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/aml-build.c | 16 ++++++++++++++--
> include/hw/acpi/aml-build.h | 2 +-
> 2 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index de19c63..22478c2 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -642,10 +642,22 @@ Aml *aml_resource_template(void)
> return var;
> }
>
> -/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer */
> -Aml *aml_buffer(void)
> +/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefBuffer
> + * Pass byte_list as NULL to request uninitialized buffer to reserve space.
> + */
> +Aml *aml_buffer(int buffer_size, uint8_t *byte_list)
> {
> + int i;
> Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
> +
> + for (i = 0; i < buffer_size; i++) {
> + if (byte_list == NULL) {
> + build_append_byte(var->buf, 0x0);
> + } else {
> + build_append_byte(var->buf, byte_list[i]);
> + }
> + }
> +
> return var;
> }
>
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index f4e678f..fac70ea 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -253,7 +253,7 @@ Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> Aml *aml_method(const char *name, int arg_count);
> Aml *aml_if(Aml *predicate);
> Aml *aml_package(uint8_t num_elements);
> -Aml *aml_buffer(void);
> +Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
> Aml *aml_resource_template(void);
> Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
> Aml *aml_varpackage(uint32_t num_elements);
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 15/24] hw/acpi/aml-build: Add ToUUID macro
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (13 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 14/24] hw/acpi/aml-build: Make aml_buffer() definition consistent with the spec Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 10:09 ` Michael S. Tsirkin
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 16/24] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
` (9 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Add ToUUID macro, this is useful for generating PCIe ACPI table.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 53 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 54 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 22478c2..ebce504 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -962,6 +962,59 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
addr_trans, len, flags);
}
+static uint8_t Hex2Byte(const char *src)
+{
+ int hi, lo;
+
+ hi = Hex2Digit(src[0]);
+ assert(hi >= 0);
+ assert(hi <= 15);
+
+ lo = Hex2Digit(src[1]);
+ assert(lo >= 0);
+ assert(lo <= 15);
+ return (hi << 4) | lo;
+}
+
+/*
+ * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
+ * e.g. UUID: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp
+ * call aml_touuid("aabbccdd-eeff-gghh-iijj-kkllmmnnoopp");
+ */
+Aml *aml_touuid(const char *uuid)
+{
+ Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
+
+ assert(strlen(uuid) == 36);
+ assert(uuid[8] == '-');
+ assert(uuid[13] == '-');
+ assert(uuid[18] == '-');
+ assert(uuid[23] == '-');
+
+ build_append_byte(var->buf, Hex2Byte(uuid + 6)); /* dd - at offset 00 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 4)); /* cc - at offset 01 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 2)); /* bb - at offset 02 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 0)); /* aa - at offset 03 */
+
+ build_append_byte(var->buf, Hex2Byte(uuid + 11)); /* ff - at offset 04 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 9)); /* ee - at offset 05 */
+
+ build_append_byte(var->buf, Hex2Byte(uuid + 16)); /* hh - at offset 06 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 14)); /* gg - at offset 07 */
+
+ build_append_byte(var->buf, Hex2Byte(uuid + 19)); /* ii - at offset 08 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 21)); /* jj - at offset 09 */
+
+ build_append_byte(var->buf, Hex2Byte(uuid + 24)); /* kk - at offset 10 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 26)); /* ll - at offset 11 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 28)); /* mm - at offset 12 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 30)); /* nn - at offset 13 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 32)); /* oo - at offset 14 */
+ build_append_byte(var->buf, Hex2Byte(uuid + 34)); /* pp - at offset 15 */
+
+ return var;
+}
+
void
build_header(GArray *linker, GArray *table_data,
AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index fac70ea..a873b46 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -257,6 +257,7 @@ Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
Aml *aml_varpackage(uint32_t num_elements);
+Aml *aml_touuid(const char *uuid);
void
build_header(GArray *linker, GArray *table_data,
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 15/24] hw/acpi/aml-build: Add ToUUID macro
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 15/24] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
@ 2015-05-27 10:09 ` Michael S. Tsirkin
0 siblings, 0 replies; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:09 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, May 25, 2015 at 10:55:11AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Add ToUUID macro, this is useful for generating PCIe ACPI table.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/aml-build.c | 53 +++++++++++++++++++++++++++++++++++++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 54 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 22478c2..ebce504 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -962,6 +962,59 @@ Aml *aml_qword_memory(AmlDecode dec, AmlMinFixed min_fixed,
> addr_trans, len, flags);
> }
>
> +static uint8_t Hex2Byte(const char *src)
> +{
> + int hi, lo;
> +
> + hi = Hex2Digit(src[0]);
> + assert(hi >= 0);
> + assert(hi <= 15);
> +
> + lo = Hex2Digit(src[1]);
> + assert(lo >= 0);
> + assert(lo <= 15);
> + return (hi << 4) | lo;
> +}
> +
> +/*
> + * ACPI 3.0: 17.5.124 ToUUID (Convert String to UUID Macro)
> + * e.g. UUID: aabbccdd-eeff-gghh-iijj-kkllmmnnoopp
> + * call aml_touuid("aabbccdd-eeff-gghh-iijj-kkllmmnnoopp");
> + */
> +Aml *aml_touuid(const char *uuid)
> +{
> + Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
> +
> + assert(strlen(uuid) == 36);
> + assert(uuid[8] == '-');
> + assert(uuid[13] == '-');
> + assert(uuid[18] == '-');
> + assert(uuid[23] == '-');
> +
> + build_append_byte(var->buf, Hex2Byte(uuid + 6)); /* dd - at offset 00 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 4)); /* cc - at offset 01 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 2)); /* bb - at offset 02 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 0)); /* aa - at offset 03 */
> +
> + build_append_byte(var->buf, Hex2Byte(uuid + 11)); /* ff - at offset 04 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 9)); /* ee - at offset 05 */
> +
> + build_append_byte(var->buf, Hex2Byte(uuid + 16)); /* hh - at offset 06 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 14)); /* gg - at offset 07 */
> +
> + build_append_byte(var->buf, Hex2Byte(uuid + 19)); /* ii - at offset 08 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 21)); /* jj - at offset 09 */
> +
> + build_append_byte(var->buf, Hex2Byte(uuid + 24)); /* kk - at offset 10 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 26)); /* ll - at offset 11 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 28)); /* mm - at offset 12 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 30)); /* nn - at offset 13 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 32)); /* oo - at offset 14 */
> + build_append_byte(var->buf, Hex2Byte(uuid + 34)); /* pp - at offset 15 */
> +
> + return var;
> +}
> +
> void
> build_header(GArray *linker, GArray *table_data,
> AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index fac70ea..a873b46 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -257,6 +257,7 @@ Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
> Aml *aml_resource_template(void);
> Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
> Aml *aml_varpackage(uint32_t num_elements);
> +Aml *aml_touuid(const char *uuid);
>
> void
> build_header(GArray *linker, GArray *table_data,
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 16/24] hw/acpi/aml-build: Add aml_or() term
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (14 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 15/24] hw/acpi/aml-build: Add ToUUID macro Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 10:09 ` Michael S. Tsirkin
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 17/24] hw/acpi/aml-build: Add aml_lnot() term Shannon Zhao
` (8 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 10 ++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index ebce504..5002ad5 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -455,6 +455,16 @@ Aml *aml_and(Aml *arg1, Aml *arg2)
return var;
}
+/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
+Aml *aml_or(Aml *arg1, Aml *arg2)
+{
+ Aml *var = aml_opcode(0x7D /* OrOp */);
+ aml_append(var, arg1);
+ aml_append(var, arg2);
+ build_append_byte(var->buf, 0x00 /* NullNameOp */);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefNotify */
Aml *aml_notify(Aml *arg1, Aml *arg2)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index a873b46..8690aeb 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -201,6 +201,7 @@ Aml *aml_int(const uint64_t val);
Aml *aml_arg(int pos);
Aml *aml_store(Aml *val, Aml *target);
Aml *aml_and(Aml *arg1, Aml *arg2);
+Aml *aml_or(Aml *arg1, Aml *arg2);
Aml *aml_notify(Aml *arg1, Aml *arg2);
Aml *aml_call1(const char *method, Aml *arg1);
Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 16/24] hw/acpi/aml-build: Add aml_or() term
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 16/24] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
@ 2015-05-27 10:09 ` Michael S. Tsirkin
0 siblings, 0 replies; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:09 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, May 25, 2015 at 10:55:12AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/aml-build.c | 10 ++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index ebce504..5002ad5 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -455,6 +455,16 @@ Aml *aml_and(Aml *arg1, Aml *arg2)
> return var;
> }
>
> +/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefOr */
> +Aml *aml_or(Aml *arg1, Aml *arg2)
> +{
> + Aml *var = aml_opcode(0x7D /* OrOp */);
> + aml_append(var, arg1);
> + aml_append(var, arg2);
> + build_append_byte(var->buf, 0x00 /* NullNameOp */);
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefNotify */
> Aml *aml_notify(Aml *arg1, Aml *arg2)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index a873b46..8690aeb 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -201,6 +201,7 @@ Aml *aml_int(const uint64_t val);
> Aml *aml_arg(int pos);
> Aml *aml_store(Aml *val, Aml *target);
> Aml *aml_and(Aml *arg1, Aml *arg2);
> +Aml *aml_or(Aml *arg1, Aml *arg2);
> Aml *aml_notify(Aml *arg1, Aml *arg2);
> Aml *aml_call1(const char *method, Aml *arg1);
> Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 17/24] hw/acpi/aml-build: Add aml_lnot() term
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (15 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 16/24] hw/acpi/aml-build: Add aml_or() term Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 10:10 ` Michael S. Tsirkin
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 18/24] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
` (7 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 8 ++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 5002ad5..56cce41 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -607,6 +607,14 @@ Aml *aml_irq_no_flags(uint8_t irq)
return var;
}
+/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLNot */
+Aml *aml_lnot(Aml *arg)
+{
+ Aml *var = aml_opcode(0x92 /* LNotOp */);
+ aml_append(var, arg);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLEqual */
Aml *aml_equal(Aml *arg1, Aml *arg2)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 8690aeb..41b2cdd 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -222,6 +222,7 @@ Aml *aml_named_field(const char *name, unsigned length);
Aml *aml_reserved_field(unsigned length);
Aml *aml_local(int num);
Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
+Aml *aml_lnot(Aml *arg);
Aml *aml_equal(Aml *arg1, Aml *arg2);
Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
const char *name_format, ...) GCC_FMT_ATTR(4, 5);
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 17/24] hw/acpi/aml-build: Add aml_lnot() term
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 17/24] hw/acpi/aml-build: Add aml_lnot() term Shannon Zhao
@ 2015-05-27 10:10 ` Michael S. Tsirkin
0 siblings, 0 replies; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:10 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, May 25, 2015 at 10:55:13AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/aml-build.c | 8 ++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 9 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 5002ad5..56cce41 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -607,6 +607,14 @@ Aml *aml_irq_no_flags(uint8_t irq)
> return var;
> }
>
> +/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLNot */
> +Aml *aml_lnot(Aml *arg)
> +{
> + Aml *var = aml_opcode(0x92 /* LNotOp */);
> + aml_append(var, arg);
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLEqual */
> Aml *aml_equal(Aml *arg1, Aml *arg2)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 8690aeb..41b2cdd 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -222,6 +222,7 @@ Aml *aml_named_field(const char *name, unsigned length);
> Aml *aml_reserved_field(unsigned length);
> Aml *aml_local(int num);
> Aml *aml_string(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> +Aml *aml_lnot(Aml *arg);
> Aml *aml_equal(Aml *arg1, Aml *arg2);
> Aml *aml_processor(uint8_t proc_id, uint32_t pblk_addr, uint8_t pblk_len,
> const char *name_format, ...) GCC_FMT_ATTR(4, 5);
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 18/24] hw/acpi/aml-build: Add aml_else() term
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (16 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 17/24] hw/acpi/aml-build: Add aml_lnot() term Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 10:10 ` Michael S. Tsirkin
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 19/24] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
` (6 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 7 +++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 8 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 56cce41..cfe1b29 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -632,6 +632,13 @@ Aml *aml_if(Aml *predicate)
return var;
}
+/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefElse */
+Aml *aml_else(void)
+{
+ Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
Aml *aml_method(const char *name, int arg_count)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 41b2cdd..c999ef1 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -254,6 +254,7 @@ Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
Aml *aml_method(const char *name, int arg_count);
Aml *aml_if(Aml *predicate);
+Aml *aml_else(void);
Aml *aml_package(uint8_t num_elements);
Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
Aml *aml_resource_template(void);
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 18/24] hw/acpi/aml-build: Add aml_else() term
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 18/24] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
@ 2015-05-27 10:10 ` Michael S. Tsirkin
0 siblings, 0 replies; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:10 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, May 25, 2015 at 10:55:14AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/aml-build.c | 7 +++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 8 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 56cce41..cfe1b29 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -632,6 +632,13 @@ Aml *aml_if(Aml *predicate)
> return var;
> }
>
> +/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefElse */
> +Aml *aml_else(void)
> +{
> + Aml *var = aml_bundle(0xA1 /* ElseOp */, AML_PACKAGE);
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefMethod */
> Aml *aml_method(const char *name, int arg_count)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 41b2cdd..c999ef1 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -254,6 +254,7 @@ Aml *aml_scope(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> Aml *aml_device(const char *name_format, ...) GCC_FMT_ATTR(1, 2);
> Aml *aml_method(const char *name, int arg_count);
> Aml *aml_if(Aml *predicate);
> +Aml *aml_else(void);
> Aml *aml_package(uint8_t num_elements);
> Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
> Aml *aml_resource_template(void);
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 19/24] hw/acpi/aml-build: Add aml_create_dword_field() term
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (17 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 18/24] hw/acpi/aml-build: Add aml_else() term Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 10:10 ` Michael S. Tsirkin
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 20/24] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
` (5 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 11 +++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index cfe1b29..2927be1 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -738,6 +738,17 @@ Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule)
return var;
}
+/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefCreateDWordField */
+Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name)
+{
+ Aml *var = aml_alloc();
+ build_append_byte(var->buf, 0x8A); /* CreateDWordFieldOp */
+ aml_append(var, srcbuf);
+ aml_append(var, index);
+ build_append_namestring(var->buf, "%s", name);
+ return var;
+}
+
/* ACPI 1.0b: 16.2.3 Data Objects Encoding: String */
Aml *aml_string(const char *name_format, ...)
{
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index c999ef1..ae62995 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -259,6 +259,7 @@ Aml *aml_package(uint8_t num_elements);
Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
Aml *aml_resource_template(void);
Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
+Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name);
Aml *aml_varpackage(uint32_t num_elements);
Aml *aml_touuid(const char *uuid);
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 19/24] hw/acpi/aml-build: Add aml_create_dword_field() term
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 19/24] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
@ 2015-05-27 10:10 ` Michael S. Tsirkin
0 siblings, 0 replies; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:10 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, May 25, 2015 at 10:55:15AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/aml-build.c | 11 +++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index cfe1b29..2927be1 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -738,6 +738,17 @@ Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule)
> return var;
> }
>
> +/* ACPI 1.0b: 16.2.5.2 Named Objects Encoding: DefCreateDWordField */
> +Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name)
> +{
> + Aml *var = aml_alloc();
> + build_append_byte(var->buf, 0x8A); /* CreateDWordFieldOp */
> + aml_append(var, srcbuf);
> + aml_append(var, index);
> + build_append_namestring(var->buf, "%s", name);
> + return var;
> +}
> +
> /* ACPI 1.0b: 16.2.3 Data Objects Encoding: String */
> Aml *aml_string(const char *name_format, ...)
> {
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index c999ef1..ae62995 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -259,6 +259,7 @@ Aml *aml_package(uint8_t num_elements);
> Aml *aml_buffer(int buffer_size, uint8_t *byte_list);
> Aml *aml_resource_template(void);
> Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
> +Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name);
> Aml *aml_varpackage(uint32_t num_elements);
> Aml *aml_touuid(const char *uuid);
>
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 20/24] hw/acpi/aml-build: Add aml_dword_io() term
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (18 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 19/24] hw/acpi/aml-build: Add aml_create_dword_field() term Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 10:10 ` Michael S. Tsirkin
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 21/24] hw/acpi/aml-build: Add Unicode macro Shannon Zhao
` (4 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 18 ++++++++++++++++++
include/hw/acpi/aml-build.h | 5 +++++
2 files changed, 23 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 2927be1..bd91981 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -959,6 +959,24 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
}
/*
+ * ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Descriptor
+ *
+ * More verbose description at:
+ * ACPI 5.0: 19.5.33 DWordIO (DWord IO Resource Descriptor Macro)
+ */
+Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
+ AmlDecode dec, AmlISARanges isa_ranges,
+ uint32_t addr_gran, uint32_t addr_min,
+ uint32_t addr_max, uint32_t addr_trans,
+ uint32_t len)
+
+{
+ return aml_dword_as_desc(AML_IO_RANGE, min_fixed, max_fixed, dec,
+ addr_gran, addr_min, addr_max, addr_trans, len,
+ isa_ranges);
+}
+
+/*
* ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Space Descriptor
*
* More verbose description at:
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index ae62995..b81c838 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -236,6 +236,11 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
uint16_t addr_gran, uint16_t addr_min,
uint16_t addr_max, uint16_t addr_trans,
uint16_t len);
+Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
+ AmlDecode dec, AmlISARanges isa_ranges,
+ uint32_t addr_gran, uint32_t addr_min,
+ uint32_t addr_max, uint32_t addr_trans,
+ uint32_t len);
Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
AmlMaxFixed max_fixed, AmlCacheable cacheable,
AmlReadAndWrite read_and_write,
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 20/24] hw/acpi/aml-build: Add aml_dword_io() term
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 20/24] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
@ 2015-05-27 10:10 ` Michael S. Tsirkin
0 siblings, 0 replies; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:10 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, May 25, 2015 at 10:55:16AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/aml-build.c | 18 ++++++++++++++++++
> include/hw/acpi/aml-build.h | 5 +++++
> 2 files changed, 23 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 2927be1..bd91981 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -959,6 +959,24 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
> }
>
> /*
> + * ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Descriptor
> + *
> + * More verbose description at:
> + * ACPI 5.0: 19.5.33 DWordIO (DWord IO Resource Descriptor Macro)
> + */
> +Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
> + AmlDecode dec, AmlISARanges isa_ranges,
> + uint32_t addr_gran, uint32_t addr_min,
> + uint32_t addr_max, uint32_t addr_trans,
> + uint32_t len)
> +
> +{
> + return aml_dword_as_desc(AML_IO_RANGE, min_fixed, max_fixed, dec,
> + addr_gran, addr_min, addr_max, addr_trans, len,
> + isa_ranges);
> +}
> +
> +/*
> * ACPI 1.0b: 6.4.3.5.4 ASL Macros for DWORD Address Space Descriptor
> *
> * More verbose description at:
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index ae62995..b81c838 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -236,6 +236,11 @@ Aml *aml_word_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
> uint16_t addr_gran, uint16_t addr_min,
> uint16_t addr_max, uint16_t addr_trans,
> uint16_t len);
> +Aml *aml_dword_io(AmlMinFixed min_fixed, AmlMaxFixed max_fixed,
> + AmlDecode dec, AmlISARanges isa_ranges,
> + uint32_t addr_gran, uint32_t addr_min,
> + uint32_t addr_max, uint32_t addr_trans,
> + uint32_t len);
> Aml *aml_dword_memory(AmlDecode dec, AmlMinFixed min_fixed,
> AmlMaxFixed max_fixed, AmlCacheable cacheable,
> AmlReadAndWrite read_and_write,
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 21/24] hw/acpi/aml-build: Add Unicode macro
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (19 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 20/24] hw/acpi/aml-build: Add aml_dword_io() term Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 10:11 ` Michael S. Tsirkin
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 22/24] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
` (3 subsequent siblings)
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
---
hw/acpi/aml-build.c | 17 +++++++++++++++++
include/hw/acpi/aml-build.h | 1 +
2 files changed, 18 insertions(+)
diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index bd91981..323b7bc 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -1069,6 +1069,23 @@ Aml *aml_touuid(const char *uuid)
return var;
}
+/*
+ * ACPI 2.0b: 16.2.3.6.4.3 Unicode Macro (Convert Ascii String To Unicode)
+ */
+Aml *aml_unicode(const char *str)
+{
+ int i = 0;
+ Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
+
+ do {
+ build_append_byte(var->buf, str[i]);
+ build_append_byte(var->buf, 0);
+ i++;
+ } while (i <= strlen(str));
+
+ return var;
+}
+
void
build_header(GArray *linker, GArray *table_data,
AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index b81c838..9773bfd 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -267,6 +267,7 @@ Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name);
Aml *aml_varpackage(uint32_t num_elements);
Aml *aml_touuid(const char *uuid);
+Aml *aml_unicode(const char *str);
void
build_header(GArray *linker, GArray *table_data,
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 21/24] hw/acpi/aml-build: Add Unicode macro
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 21/24] hw/acpi/aml-build: Add Unicode macro Shannon Zhao
@ 2015-05-27 10:11 ` Michael S. Tsirkin
0 siblings, 0 replies; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:11 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo, imammedo,
pbonzini, lersek, christoffer.dall, shannon.zhao
On Mon, May 25, 2015 at 10:55:17AM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> ---
> hw/acpi/aml-build.c | 17 +++++++++++++++++
> include/hw/acpi/aml-build.h | 1 +
> 2 files changed, 18 insertions(+)
>
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index bd91981..323b7bc 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -1069,6 +1069,23 @@ Aml *aml_touuid(const char *uuid)
> return var;
> }
>
> +/*
> + * ACPI 2.0b: 16.2.3.6.4.3 Unicode Macro (Convert Ascii String To Unicode)
> + */
> +Aml *aml_unicode(const char *str)
> +{
> + int i = 0;
> + Aml *var = aml_bundle(0x11 /* BufferOp */, AML_BUFFER);
> +
> + do {
> + build_append_byte(var->buf, str[i]);
> + build_append_byte(var->buf, 0);
> + i++;
> + } while (i <= strlen(str));
> +
> + return var;
> +}
> +
> void
> build_header(GArray *linker, GArray *table_data,
> AcpiTableHeader *h, const char *sig, int len, uint8_t rev)
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index b81c838..9773bfd 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -267,6 +267,7 @@ Aml *aml_field(const char *name, AmlAccessType type, AmlUpdateRule rule);
> Aml *aml_create_dword_field(Aml *srcbuf, Aml *index, const char *name);
> Aml *aml_varpackage(uint32_t num_elements);
> Aml *aml_touuid(const char *uuid);
> +Aml *aml_unicode(const char *str);
>
> void
> build_header(GArray *linker, GArray *table_data,
> --
> 2.0.4
>
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 22/24] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (20 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 21/24] hw/acpi/aml-build: Add Unicode macro Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 23/24] ACPI: split CONFIG_ACPI into 4 pieces Shannon Zhao
` (2 subsequent siblings)
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Add PCIe controller in ACPI DSDT table, so the guest can detect
the PCIe.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt-acpi-build.c | 154 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 154 insertions(+)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 95c83ee..a9373cc 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -40,6 +40,7 @@
#include "hw/hw.h"
#include "hw/acpi/aml-build.h"
#include "hw/pci/pcie_host.h"
+#include "hw/pci/pci.h"
#define ARM_SPI_BASE 32
@@ -152,6 +153,157 @@ static void acpi_dsdt_add_virtio(Aml *scope,
}
}
+static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, int irq)
+{
+ Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf;
+ int i, bus_no;
+ hwaddr base_mmio = memmap[VIRT_PCIE_MMIO].base;
+ hwaddr size_mmio = memmap[VIRT_PCIE_MMIO].size;
+ hwaddr base_pio = memmap[VIRT_PCIE_PIO].base;
+ hwaddr size_pio = memmap[VIRT_PCIE_PIO].size;
+ hwaddr base_ecam = memmap[VIRT_PCIE_ECAM].base;
+ hwaddr size_ecam = memmap[VIRT_PCIE_ECAM].size;
+ int nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
+
+ Aml *dev = aml_device("%s", "PCI0");
+ aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08")));
+ aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03")));
+ aml_append(dev, aml_name_decl("_SEG", aml_int(0)));
+ aml_append(dev, aml_name_decl("_BBN", aml_int(0)));
+ aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, aml_name_decl("_UID", aml_string("PCI0")));
+ aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device")));
+
+ /* Declare the PCI Routing Table. */
+ Aml *rt_pkg = aml_package(nr_pcie_buses * PCI_NUM_PINS);
+ for (bus_no = 0; bus_no < nr_pcie_buses; bus_no++) {
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ int gsi = (i + bus_no) % PCI_NUM_PINS;
+ Aml *pkg = aml_package(4);
+ aml_append(pkg, aml_int((bus_no << 16) | 0xFFFF));
+ aml_append(pkg, aml_int(i));
+ aml_append(pkg, aml_name("GSI%d", gsi));
+ aml_append(pkg, aml_int(0));
+ aml_append(rt_pkg, pkg);
+ }
+ }
+ aml_append(dev, aml_name_decl("_PRT", rt_pkg));
+
+ /* Create GSI link device */
+ for (i = 0; i < PCI_NUM_PINS; i++) {
+ Aml *dev_gsi = aml_device("GSI%d", i);
+ aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F")));
+ aml_append(dev_gsi, aml_name_decl("_UID", aml_int(0)));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, irq + i));
+ aml_append(dev_gsi, aml_name_decl("_PRS", crs));
+ crs = aml_resource_template();
+ aml_append(crs,
+ aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ AML_EXCLUSIVE, irq + i));
+ aml_append(dev_gsi, aml_name_decl("_CRS", crs));
+ method = aml_method("_SRS", 1);
+ aml_append(dev_gsi, method);
+ aml_append(dev, dev_gsi);
+ }
+
+ method = aml_method("_CBA", 0);
+ aml_append(method, aml_return(aml_int(base_ecam)));
+ aml_append(dev, method);
+
+ method = aml_method("_CRS", 0);
+ Aml *rbuf = aml_resource_template();
+ aml_append(rbuf,
+ aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000,
+ nr_pcie_buses));
+ aml_append(rbuf,
+ aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
+ AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio,
+ base_mmio + size_mmio - 1, 0x0000, size_mmio));
+ aml_append(rbuf,
+ aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
+ AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_pio,
+ size_pio));
+
+ aml_append(method, aml_name_decl("RBUF", rbuf));
+ aml_append(method, aml_return(rbuf));
+ aml_append(dev, method);
+
+ /* Declare an _OSC (OS Control Handoff) method */
+ aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
+ aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
+ method = aml_method("_OSC", 4);
+ aml_append(method,
+ aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
+
+ /* PCI Firmware Specification 3.0
+ * 4.5.1. _OSC Interface for PCI Host Bridge Devices
+ * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is
+ * identified by the Universal Unique IDentifier (UUID)
+ * 33DB4D5B-1FF7-401C-9657-7441C03DD766
+ */
+ UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766");
+ ifctx = aml_if(aml_equal(aml_arg(0), UUID));
+ aml_append(ifctx,
+ aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
+ aml_append(ifctx,
+ aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
+ aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
+ aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL")));
+ aml_append(ifctx, aml_store(aml_and(aml_name("CTRL"), aml_int(0x1D)),
+ aml_name("CTRL")));
+
+ ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1))));
+ aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x08)),
+ aml_name("CDW1")));
+ aml_append(ifctx, ifctx1);
+
+ ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL"))));
+ aml_append(ifctx1, aml_store(aml_or(aml_name("CDW1"), aml_int(0x10)),
+ aml_name("CDW1")));
+ aml_append(ifctx, ifctx1);
+
+ aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3")));
+ aml_append(ifctx, aml_return(aml_arg(3)));
+ aml_append(method, ifctx);
+
+ elsectx = aml_else();
+ aml_append(elsectx, aml_store(aml_or(aml_name("CDW1"), aml_int(4)),
+ aml_name("CDW1")));
+ aml_append(elsectx, aml_return(aml_arg(3)));
+ aml_append(method, elsectx);
+ aml_append(dev, method);
+
+ method = aml_method("_DSM", 4);
+
+ /* PCI Firmware Specification 3.0
+ * 4.6.1. _DSM for PCI Express Slot Information
+ * The UUID in _DSM in this context is
+ * {E5C937D0-3553-4D7A-9117-EA4D19C3434D}
+ */
+ UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
+ ifctx = aml_if(aml_equal(aml_arg(0), UUID));
+ ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0)));
+ uint8_t byte_list[1] = {1};
+ buf = aml_buffer(1, byte_list);
+ aml_append(ifctx1, aml_return(buf));
+ aml_append(ifctx, ifctx1);
+ aml_append(method, ifctx);
+
+ byte_list[0] = 0;
+ buf = aml_buffer(1, byte_list);
+ aml_append(method, aml_return(buf));
+ aml_append(dev, method);
+
+ Aml *dev_rp0 = aml_device("%s", "RP0");
+ aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0)));
+ aml_append(dev, dev_rp0);
+ aml_append(scope, dev);
+}
+
/* RSDP */
static GArray *
build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
@@ -309,6 +461,8 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
+ acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE));
+
aml_append(dsdt, scope);
/* copy AML table into ACPI tables blob and patch header there */
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* [Qemu-devel] [PATCH v9 23/24] ACPI: split CONFIG_ACPI into 4 pieces
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (21 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 22/24] hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 8:37 ` Alex Bennée
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 24/24] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables Shannon Zhao
2015-05-27 9:43 ` [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Igor Mammedov
24 siblings, 1 reply; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
As core.c, piix4.c, ich9.c and pcihp.c are for x86, add CONFIG_ACPI_X86
to make it only for x86. ARM doesn't support cpu and memory hotplug, add
CONFIG_ACPI_CPU_HOTPLUG and CONFIG_ACPI_MEMORY_HOTPLUG to exclude them
for target-arm.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
default-configs/arm-softmmu.mak | 1 +
default-configs/i386-softmmu.mak | 3 +++
default-configs/mips-softmmu.mak | 3 +++
default-configs/mips64-softmmu.mak | 3 +++
default-configs/mips64el-softmmu.mak | 3 +++
default-configs/mipsel-softmmu.mak | 3 +++
default-configs/x86_64-softmmu.mak | 3 +++
hw/acpi/Makefile.objs | 5 +++--
hw/i2c/Makefile.objs | 2 +-
9 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index a767e4b..74f1db3 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -101,3 +101,4 @@ CONFIG_ALLWINNER_A10=y
CONFIG_XIO3130=y
CONFIG_IOH3420=y
CONFIG_I82801B11=y
+CONFIG_ACPI=y
diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
index 6a74e00..91d602c 100644
--- a/default-configs/i386-softmmu.mak
+++ b/default-configs/i386-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_X86=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_IDE_ISA=y
diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-softmmu.mak
index cce2c81..fd0607d 100644
--- a/default-configs/mips-softmmu.mak
+++ b/default-configs/mips-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_X86=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-softmmu.mak
index 7a88a08..b8c7910 100644
--- a/default-configs/mips64-softmmu.mak
+++ b/default-configs/mips64-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_X86=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak
index 095de43..ae4274b 100644
--- a/default-configs/mips64el-softmmu.mak
+++ b/default-configs/mips64el-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_X86=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-softmmu.mak
index 0e25108..1e2374b 100644
--- a/default-configs/mipsel-softmmu.mak
+++ b/default-configs/mipsel-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_X86=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_PIIX4=y
diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
index 46b87dd..2f2955b 100644
--- a/default-configs/x86_64-softmmu.mak
+++ b/default-configs/x86_64-softmmu.mak
@@ -15,6 +15,9 @@ CONFIG_PCSPK=y
CONFIG_PCKBD=y
CONFIG_FDC=y
CONFIG_ACPI=y
+CONFIG_ACPI_X86=y
+CONFIG_ACPI_MEMORY_HOTPLUG=y
+CONFIG_ACPI_CPU_HOTPLUG=y
CONFIG_APM=y
CONFIG_I8257=y
CONFIG_IDE_ISA=y
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index b9fefa7..29d46d8 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -1,5 +1,6 @@
-common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o pcihp.o cpu_hotplug.o
-common-obj-$(CONFIG_ACPI) += memory_hotplug.o
+common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o ich9.o pcihp.o
+common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
+common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
common-obj-$(CONFIG_ACPI) += acpi_interface.o
common-obj-$(CONFIG_ACPI) += bios-linker-loader.o
common-obj-$(CONFIG_ACPI) += aml-build.o
diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
index 648278e..0f13060 100644
--- a/hw/i2c/Makefile.objs
+++ b/hw/i2c/Makefile.objs
@@ -1,6 +1,6 @@
common-obj-y += core.o smbus.o smbus_eeprom.o
common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
-common-obj-$(CONFIG_ACPI) += smbus_ich9.o
+common-obj-$(CONFIG_ACPI_X86) += smbus_ich9.o
common-obj-$(CONFIG_APM) += pm_smbus.o
common-obj-$(CONFIG_BITBANG_I2C) += bitbang_i2c.o
common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 23/24] ACPI: split CONFIG_ACPI into 4 pieces
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 23/24] ACPI: split CONFIG_ACPI into 4 pieces Shannon Zhao
@ 2015-05-27 8:37 ` Alex Bennée
0 siblings, 0 replies; 53+ messages in thread
From: Alex Bennée @ 2015-05-27 8:37 UTC (permalink / raw)
To: Shannon Zhao
Cc: peter.maydell, hangaohuai, mst, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, hanjun.guo, imammedo, pbonzini,
lersek, christoffer.dall, shannon.zhao
Shannon Zhao <zhaoshenglong@huawei.com> writes:
> From: Shannon Zhao <shannon.zhao@linaro.org>
>
> As core.c, piix4.c, ich9.c and pcihp.c are for x86, add CONFIG_ACPI_X86
> to make it only for x86. ARM doesn't support cpu and memory hotplug, add
> CONFIG_ACPI_CPU_HOTPLUG and CONFIG_ACPI_MEMORY_HOTPLUG to exclude them
> for target-arm.
>
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
The fact a file named "core.c" is x86 only causes me slight cognitive
dissonance but whatever ;-)
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
> ---
> default-configs/arm-softmmu.mak | 1 +
> default-configs/i386-softmmu.mak | 3 +++
> default-configs/mips-softmmu.mak | 3 +++
> default-configs/mips64-softmmu.mak | 3 +++
> default-configs/mips64el-softmmu.mak | 3 +++
> default-configs/mipsel-softmmu.mak | 3 +++
> default-configs/x86_64-softmmu.mak | 3 +++
> hw/acpi/Makefile.objs | 5 +++--
> hw/i2c/Makefile.objs | 2 +-
> 9 files changed, 23 insertions(+), 3 deletions(-)
>
> diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
> index a767e4b..74f1db3 100644
> --- a/default-configs/arm-softmmu.mak
> +++ b/default-configs/arm-softmmu.mak
> @@ -101,3 +101,4 @@ CONFIG_ALLWINNER_A10=y
> CONFIG_XIO3130=y
> CONFIG_IOH3420=y
> CONFIG_I82801B11=y
> +CONFIG_ACPI=y
> diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak
> index 6a74e00..91d602c 100644
> --- a/default-configs/i386-softmmu.mak
> +++ b/default-configs/i386-softmmu.mak
> @@ -15,6 +15,9 @@ CONFIG_PCSPK=y
> CONFIG_PCKBD=y
> CONFIG_FDC=y
> CONFIG_ACPI=y
> +CONFIG_ACPI_X86=y
> +CONFIG_ACPI_MEMORY_HOTPLUG=y
> +CONFIG_ACPI_CPU_HOTPLUG=y
> CONFIG_APM=y
> CONFIG_I8257=y
> CONFIG_IDE_ISA=y
> diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-softmmu.mak
> index cce2c81..fd0607d 100644
> --- a/default-configs/mips-softmmu.mak
> +++ b/default-configs/mips-softmmu.mak
> @@ -15,6 +15,9 @@ CONFIG_PCSPK=y
> CONFIG_PCKBD=y
> CONFIG_FDC=y
> CONFIG_ACPI=y
> +CONFIG_ACPI_X86=y
> +CONFIG_ACPI_MEMORY_HOTPLUG=y
> +CONFIG_ACPI_CPU_HOTPLUG=y
> CONFIG_APM=y
> CONFIG_I8257=y
> CONFIG_PIIX4=y
> diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-softmmu.mak
> index 7a88a08..b8c7910 100644
> --- a/default-configs/mips64-softmmu.mak
> +++ b/default-configs/mips64-softmmu.mak
> @@ -15,6 +15,9 @@ CONFIG_PCSPK=y
> CONFIG_PCKBD=y
> CONFIG_FDC=y
> CONFIG_ACPI=y
> +CONFIG_ACPI_X86=y
> +CONFIG_ACPI_MEMORY_HOTPLUG=y
> +CONFIG_ACPI_CPU_HOTPLUG=y
> CONFIG_APM=y
> CONFIG_I8257=y
> CONFIG_PIIX4=y
> diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak
> index 095de43..ae4274b 100644
> --- a/default-configs/mips64el-softmmu.mak
> +++ b/default-configs/mips64el-softmmu.mak
> @@ -15,6 +15,9 @@ CONFIG_PCSPK=y
> CONFIG_PCKBD=y
> CONFIG_FDC=y
> CONFIG_ACPI=y
> +CONFIG_ACPI_X86=y
> +CONFIG_ACPI_MEMORY_HOTPLUG=y
> +CONFIG_ACPI_CPU_HOTPLUG=y
> CONFIG_APM=y
> CONFIG_I8257=y
> CONFIG_PIIX4=y
> diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-softmmu.mak
> index 0e25108..1e2374b 100644
> --- a/default-configs/mipsel-softmmu.mak
> +++ b/default-configs/mipsel-softmmu.mak
> @@ -15,6 +15,9 @@ CONFIG_PCSPK=y
> CONFIG_PCKBD=y
> CONFIG_FDC=y
> CONFIG_ACPI=y
> +CONFIG_ACPI_X86=y
> +CONFIG_ACPI_MEMORY_HOTPLUG=y
> +CONFIG_ACPI_CPU_HOTPLUG=y
> CONFIG_APM=y
> CONFIG_I8257=y
> CONFIG_PIIX4=y
> diff --git a/default-configs/x86_64-softmmu.mak b/default-configs/x86_64-softmmu.mak
> index 46b87dd..2f2955b 100644
> --- a/default-configs/x86_64-softmmu.mak
> +++ b/default-configs/x86_64-softmmu.mak
> @@ -15,6 +15,9 @@ CONFIG_PCSPK=y
> CONFIG_PCKBD=y
> CONFIG_FDC=y
> CONFIG_ACPI=y
> +CONFIG_ACPI_X86=y
> +CONFIG_ACPI_MEMORY_HOTPLUG=y
> +CONFIG_ACPI_CPU_HOTPLUG=y
> CONFIG_APM=y
> CONFIG_I8257=y
> CONFIG_IDE_ISA=y
> diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
> index b9fefa7..29d46d8 100644
> --- a/hw/acpi/Makefile.objs
> +++ b/hw/acpi/Makefile.objs
> @@ -1,5 +1,6 @@
> -common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o pcihp.o cpu_hotplug.o
> -common-obj-$(CONFIG_ACPI) += memory_hotplug.o
> +common-obj-$(CONFIG_ACPI_X86) += core.o piix4.o ich9.o pcihp.o
> +common-obj-$(CONFIG_ACPI_CPU_HOTPLUG) += cpu_hotplug.o
> +common-obj-$(CONFIG_ACPI_MEMORY_HOTPLUG) += memory_hotplug.o
> common-obj-$(CONFIG_ACPI) += acpi_interface.o
> common-obj-$(CONFIG_ACPI) += bios-linker-loader.o
> common-obj-$(CONFIG_ACPI) += aml-build.o
> diff --git a/hw/i2c/Makefile.objs b/hw/i2c/Makefile.objs
> index 648278e..0f13060 100644
> --- a/hw/i2c/Makefile.objs
> +++ b/hw/i2c/Makefile.objs
> @@ -1,6 +1,6 @@
> common-obj-y += core.o smbus.o smbus_eeprom.o
> common-obj-$(CONFIG_VERSATILE_I2C) += versatile_i2c.o
> -common-obj-$(CONFIG_ACPI) += smbus_ich9.o
> +common-obj-$(CONFIG_ACPI_X86) += smbus_ich9.o
> common-obj-$(CONFIG_APM) += pm_smbus.o
> common-obj-$(CONFIG_BITBANG_I2C) += bitbang_i2c.o
> common-obj-$(CONFIG_EXYNOS4) += exynos4210_i2c.o
--
Alex Bennée
^ permalink raw reply [flat|nested] 53+ messages in thread
* [Qemu-devel] [PATCH v9 24/24] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (22 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 23/24] ACPI: split CONFIG_ACPI into 4 pieces Shannon Zhao
@ 2015-05-25 2:55 ` Shannon Zhao
2015-05-27 9:43 ` [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Igor Mammedov
24 siblings, 0 replies; 53+ messages in thread
From: Shannon Zhao @ 2015-05-25 2:55 UTC (permalink / raw)
To: qemu-devel, peter.maydell, pbonzini, christoffer.dall,
a.spyridakis, claudio.fontana, imammedo, hanjun.guo, mst, lersek,
alex.bennee
Cc: hangaohuai, zhaoshenglong, peter.huangpeng, shannon.zhao
From: Shannon Zhao <shannon.zhao@linaro.org>
Initialize VirtGuestInfoState and register a machine_init_done notify to
call virt_acpi_build().
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
hw/arm/virt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a6a399d..05db8cb 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -44,6 +44,7 @@
#include "qemu/bitops.h"
#include "qemu/error-report.h"
#include "hw/pci-host/gpex.h"
+#include "hw/arm/virt-acpi-build.h"
/* Number of external interrupt lines to configure the GIC with */
#define NUM_IRQS 128
@@ -697,6 +698,14 @@ static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
return board->fdt;
}
+static
+void virt_guest_info_machine_done(Notifier *notifier, void *data)
+{
+ VirtGuestInfoState *guest_info_state = container_of(notifier,
+ VirtGuestInfoState, machine_done);
+ virt_acpi_setup(&guest_info_state->info);
+}
+
static void machvirt_init(MachineState *machine)
{
VirtMachineState *vms = VIRT_MACHINE(machine);
@@ -706,6 +715,8 @@ static void machvirt_init(MachineState *machine)
MemoryRegion *ram = g_new(MemoryRegion, 1);
const char *cpu_model = machine->cpu_model;
VirtBoardInfo *vbi;
+ VirtGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
+ VirtGuestInfo *guest_info = &guest_info_state->info;
uint32_t gic_phandle;
char **cpustr;
@@ -798,6 +809,14 @@ static void machvirt_init(MachineState *machine)
create_virtio_devices(vbi, pic);
create_fw_cfg(vbi);
+ rom_set_fw(fw_cfg_find());
+
+ guest_info->smp_cpus = smp_cpus;
+ guest_info->fw_cfg = fw_cfg_find();
+ guest_info->memmap = vbi->memmap;
+ guest_info->irqmap = vbi->irqmap;
+ guest_info_state->machine_done.notify = virt_guest_info_machine_done;
+ qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
vbi->bootinfo.ram_size = machine->ram_size;
vbi->bootinfo.kernel_filename = machine->kernel_filename;
--
2.0.4
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-05-25 2:54 [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Shannon Zhao
` (23 preceding siblings ...)
2015-05-25 2:55 ` [Qemu-devel] [PATCH v9 24/24] hw/arm/virt: Enable dynamic generation of ACPI v5.1 tables Shannon Zhao
@ 2015-05-27 9:43 ` Igor Mammedov
2015-05-27 10:16 ` Michael S. Tsirkin
24 siblings, 1 reply; 53+ messages in thread
From: Igor Mammedov @ 2015-05-27 9:43 UTC (permalink / raw)
To: peter.maydell
Cc: hangaohuai, mst, a.spyridakis, claudio.fontana, qemu-devel,
peter.huangpeng, alex.bennee, hanjun.guo, Shannon Zhao, pbonzini,
lersek, christoffer.dall, shannon.zhao
On Mon, 25 May 2015 10:54:56 +0800
Shannon Zhao <zhaoshenglong@huawei.com> wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
...
> Shannon Zhao (24):
> hw/acpi/aml-build: Make enum values to be upper case to match coding
> style
...
> hw/acpi/aml-build: Add aml_memory32_fixed() term
> hw/acpi/aml-build: Add aml_interrupt() term
...
> hw/acpi/aml-build: Make aml_buffer() definition consistent with the
> spec
> hw/acpi/aml-build: Add ToUUID macro
> hw/acpi/aml-build: Add aml_or() term
> hw/acpi/aml-build: Add aml_lnot() term
> hw/acpi/aml-build: Add aml_else() term
> hw/acpi/aml-build: Add aml_create_dword_field() term
> hw/acpi/aml-build: Add aml_dword_io() term
> hw/acpi/aml-build: Add Unicode macro
> hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
...
Peter could you apply following AML patches to master,
that would help to avoid conflicts with other series in flight
which are trying to extend AML API and make this and that series
smaller on respin.
^ permalink raw reply [flat|nested] 53+ messages in thread* Re: [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-05-27 9:43 ` [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM Igor Mammedov
@ 2015-05-27 10:16 ` Michael S. Tsirkin
2015-05-27 11:58 ` Peter Maydell
0 siblings, 1 reply; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 10:16 UTC (permalink / raw)
To: Igor Mammedov
Cc: peter.maydell, hangaohuai, a.spyridakis, claudio.fontana,
qemu-devel, peter.huangpeng, alex.bennee, hanjun.guo,
Shannon Zhao, pbonzini, lersek, christoffer.dall, shannon.zhao
On Wed, May 27, 2015 at 11:43:31AM +0200, Igor Mammedov wrote:
> On Mon, 25 May 2015 10:54:56 +0800
> Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>
> > From: Shannon Zhao <shannon.zhao@linaro.org>
> ...
> > Shannon Zhao (24):
> > hw/acpi/aml-build: Make enum values to be upper case to match coding
> > style
> ...
> > hw/acpi/aml-build: Add aml_memory32_fixed() term
> > hw/acpi/aml-build: Add aml_interrupt() term
> ...
> > hw/acpi/aml-build: Make aml_buffer() definition consistent with the
> > spec
> > hw/acpi/aml-build: Add ToUUID macro
> > hw/acpi/aml-build: Add aml_or() term
> > hw/acpi/aml-build: Add aml_lnot() term
> > hw/acpi/aml-build: Add aml_else() term
> > hw/acpi/aml-build: Add aml_create_dword_field() term
> > hw/acpi/aml-build: Add aml_dword_io() term
> > hw/acpi/aml-build: Add Unicode macro
> > hw/arm/virt-acpi-build: Add PCIe controller in ACPI DSDT table
> ...
>
> Peter could you apply following AML patches to master,
> that would help to avoid conflicts with other series in flight
> which are trying to extend AML API and make this and that series
> smaller on respin.
I'm fine with this, sent Reviewed-by tags.
Or if you want me to apply just AML patches in my tree, let me know.
--
MST
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-05-27 10:16 ` Michael S. Tsirkin
@ 2015-05-27 11:58 ` Peter Maydell
2015-05-27 12:01 ` Michael S. Tsirkin
0 siblings, 1 reply; 53+ messages in thread
From: Peter Maydell @ 2015-05-27 11:58 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: hangaohuai, Alexander Spyridakis, Shannon Zhao, Claudio Fontana,
QEMU Developers, Huangpeng (Peter), Alex Bennée, Hanjun Guo,
Paolo Bonzini, Igor Mammedov, Laszlo Ersek, Christoffer Dall,
Shannon Zhao
On 27 May 2015 at 11:16, Michael S. Tsirkin <mst@redhat.com> wrote:
> On Wed, May 27, 2015 at 11:43:31AM +0200, Igor Mammedov wrote:
>> Peter could you apply following AML patches to master,
>> that would help to avoid conflicts with other series in flight
>> which are trying to extend AML API and make this and that series
>> smaller on respin.
>
> I'm fine with this, sent Reviewed-by tags.
> Or if you want me to apply just AML patches in my tree, let me know.
I would prefer a pull request with the relevant patches in them.
Directly applying patches to master requires that I personally
review and test them...
thanks
-- PMM
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-05-27 11:58 ` Peter Maydell
@ 2015-05-27 12:01 ` Michael S. Tsirkin
2015-05-27 12:07 ` Peter Maydell
0 siblings, 1 reply; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 12:01 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Alexander Spyridakis, Shannon Zhao, Claudio Fontana,
QEMU Developers, Huangpeng (Peter), Alex Bennée, Hanjun Guo,
Paolo Bonzini, Igor Mammedov, Laszlo Ersek, Christoffer Dall,
Shannon Zhao
On Wed, May 27, 2015 at 12:58:19PM +0100, Peter Maydell wrote:
> On 27 May 2015 at 11:16, Michael S. Tsirkin <mst@redhat.com> wrote:
> > On Wed, May 27, 2015 at 11:43:31AM +0200, Igor Mammedov wrote:
> >> Peter could you apply following AML patches to master,
> >> that would help to avoid conflicts with other series in flight
> >> which are trying to extend AML API and make this and that series
> >> smaller on respin.
> >
> > I'm fine with this, sent Reviewed-by tags.
> > Or if you want me to apply just AML patches in my tree, let me know.
>
> I would prefer a pull request with the relevant patches in them.
> Directly applying patches to master requires that I personally
> review and test them...
>
> thanks
> -- PMM
How about this: separate acpi patches, I'll apply them and send
pull request. Then you can review and merge arm patches at leasure.
--
MST
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-05-27 12:01 ` Michael S. Tsirkin
@ 2015-05-27 12:07 ` Peter Maydell
2015-05-27 14:07 ` Michael S. Tsirkin
0 siblings, 1 reply; 53+ messages in thread
From: Peter Maydell @ 2015-05-27 12:07 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: hangaohuai, Alexander Spyridakis, Shannon Zhao, Claudio Fontana,
QEMU Developers, Huangpeng (Peter), Alex Bennée, Hanjun Guo,
Paolo Bonzini, Igor Mammedov, Laszlo Ersek, Christoffer Dall,
Shannon Zhao
On 27 May 2015 at 13:01, Michael S. Tsirkin <mst@redhat.com> wrote:
> How about this: separate acpi patches, I'll apply them and send
> pull request. Then you can review and merge arm patches at leasure.
As far as the ARM patches in this series are concerned, I'm
basically happy with them for a while now and have just been
waiting for the ACPI side to be reviewed...
-- PMM
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-05-27 12:07 ` Peter Maydell
@ 2015-05-27 14:07 ` Michael S. Tsirkin
2015-05-28 14:46 ` Peter Maydell
0 siblings, 1 reply; 53+ messages in thread
From: Michael S. Tsirkin @ 2015-05-27 14:07 UTC (permalink / raw)
To: Peter Maydell
Cc: hangaohuai, Alexander Spyridakis, Shannon Zhao, Claudio Fontana,
QEMU Developers, Huangpeng (Peter), Alex Bennée, Hanjun Guo,
Paolo Bonzini, Igor Mammedov, Laszlo Ersek, Christoffer Dall,
Shannon Zhao
On Wed, May 27, 2015 at 01:07:23PM +0100, Peter Maydell wrote:
> On 27 May 2015 at 13:01, Michael S. Tsirkin <mst@redhat.com> wrote:
> > How about this: separate acpi patches, I'll apply them and send
> > pull request. Then you can review and merge arm patches at leasure.
>
> As far as the ARM patches in this series are concerned, I'm
> basically happy with them for a while now and have just been
> waiting for the ACPI side to be reviewed...
>
> -- PMM
OK I did that now.
How would you like it all merged?
Your tree?
--
MST
^ permalink raw reply [flat|nested] 53+ messages in thread
* Re: [Qemu-devel] [PATCH v9 00/24] Generate ACPI v5.1 tables and expose them to guest over fw_cfg on ARM
2015-05-27 14:07 ` Michael S. Tsirkin
@ 2015-05-28 14:46 ` Peter Maydell
0 siblings, 0 replies; 53+ messages in thread
From: Peter Maydell @ 2015-05-28 14:46 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: hangaohuai, Alexander Spyridakis, Shannon Zhao, Claudio Fontana,
QEMU Developers, Huangpeng (Peter), Alex Bennée, Hanjun Guo,
Paolo Bonzini, Igor Mammedov, Laszlo Ersek, Christoffer Dall,
Shannon Zhao
On 27 May 2015 at 15:07, Michael S. Tsirkin <mst@redhat.com> wrote:
> On Wed, May 27, 2015 at 01:07:23PM +0100, Peter Maydell wrote:
>> On 27 May 2015 at 13:01, Michael S. Tsirkin <mst@redhat.com> wrote:
>> > How about this: separate acpi patches, I'll apply them and send
>> > pull request. Then you can review and merge arm patches at leasure.
>>
>> As far as the ARM patches in this series are concerned, I'm
>> basically happy with them for a while now and have just been
>> waiting for the ACPI side to be reviewed...
> OK I did that now.
> How would you like it all merged?
> Your tree?
Seems easiest. Applied all to target-arm.next; expect a pull
request to go through tail end of this week or possibly Monday.
-- PMM
^ permalink raw reply [flat|nested] 53+ messages in thread