From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxqSR-0005A7-8h for qemu-devel@nongnu.org; Thu, 28 May 2015 01:34:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxqSN-0005Fc-PY for qemu-devel@nongnu.org; Thu, 28 May 2015 01:34:19 -0400 Received: from mail-bn1bon0078.outbound.protection.outlook.com ([157.56.111.78]:20376 helo=na01-bn1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxqSN-0005FI-Ld for qemu-devel@nongnu.org; Thu, 28 May 2015 01:34:15 -0400 Date: Thu, 28 May 2015 15:30:18 +1000 From: "Edgar E. Iglesias" Message-ID: <20150528053018.GH30952@toto> References: <1432060414-5195-1-git-send-email-peter.maydell@linaro.org> <1432060414-5195-4-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1432060414-5195-4-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 03/14] target-arm: Set correct syndrome for faults on MSR DAIF*, imm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: agraf@suse.de, serge.fdrv@gmail.com, alex.bennee@linaro.org, qemu-devel@nongnu.org, patches@linaro.org On Tue, May 19, 2015 at 07:33:23PM +0100, Peter Maydell wrote: > If the SCTLR.UMA trap bit is set then attempts by EL0 to update > the PSTATE DAIF bits via "MSR DAIFSet, imm" and "MSR DAIFClr, imm" > instructions will raise an exception. We were failing to set > the syndrome information for this exception, which meant that > it would be reported as a repeat of whatever the previous > exception was. Set the correct syndrome information. > --- > target-arm/op_helper.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c > index 43e3457..5af4a0e 100644 > --- a/target-arm/op_helper.c > +++ b/target-arm/op_helper.c > @@ -381,6 +381,9 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) > */ > if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { > env->exception.target_el = exception_target_el(env); > + env->exception.syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3), > + extract32(op, 3, 3), 4, > + 0x1f, imm, 0); Did you possibly reverse the argument order of 0x1f and imm? Cheers, Edgar > raise_exception(env, EXCP_UDEF); > } > > -- > 1.9.1 >