From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxqoX-0004QJ-8R for qemu-devel@nongnu.org; Thu, 28 May 2015 01:57:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YxqoT-0002UA-Nz for qemu-devel@nongnu.org; Thu, 28 May 2015 01:57:09 -0400 Received: from mail-bl2on0072.outbound.protection.outlook.com ([65.55.169.72]:14976 helo=na01-bl2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxqoT-0002T2-Jx for qemu-devel@nongnu.org; Thu, 28 May 2015 01:57:05 -0400 Date: Thu, 28 May 2015 15:53:09 +1000 From: "Edgar E. Iglesias" Message-ID: <20150528055309.GN30952@toto> References: <1432060414-5195-1-git-send-email-peter.maydell@linaro.org> <1432060414-5195-13-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1432060414-5195-13-git-send-email-peter.maydell@linaro.org> Subject: Re: [Qemu-devel] [PATCH 12/14] target-arm: Move TB flags down to fill gap List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: agraf@suse.de, serge.fdrv@gmail.com, alex.bennee@linaro.org, qemu-devel@nongnu.org, patches@linaro.org On Tue, May 19, 2015 at 07:33:32PM +0100, Peter Maydell wrote: > Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the > bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and > ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. > > Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias > --- > target-arm/cpu.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 647e0ba..dd7a90b 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -1761,13 +1761,13 @@ static inline bool arm_singlestep_active(CPUARMState *env) > /* We store the bottom two bits of the CPAR as TB flags and handle > * checks on the other bits at runtime > */ > -#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20 > +#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17 > #define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT) > /* Indicates whether cp register reads and writes by guest code should access > * the secure or nonsecure bank of banked registers; note that this is not > * the same thing as the current security state of the processor! > */ > -#define ARM_TBFLAG_NS_SHIFT 22 > +#define ARM_TBFLAG_NS_SHIFT 19 > #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) > > /* Bit usage when in AArch64 state: currently we have no A64 specific bits */ > -- > 1.9.1 >