From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58048) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YxraA-0006RA-5e for qemu-devel@nongnu.org; Thu, 28 May 2015 02:46:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yxra6-0003x3-4q for qemu-devel@nongnu.org; Thu, 28 May 2015 02:46:22 -0400 Received: from mail-bn1on0084.outbound.protection.outlook.com ([157.56.110.84]:35264 helo=na01-bn1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yxra5-0003ws-TR for qemu-devel@nongnu.org; Thu, 28 May 2015 02:46:18 -0400 Date: Thu, 28 May 2015 16:42:20 +1000 From: "Edgar E. Iglesias" Message-ID: <20150528064220.GT30952@toto> References: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v2 2/5] target-microblaze: Preserve the pvr registers during reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis Cc: peter.crosthwaite@xilinx.com, qemu-devel@nongnu.org, afaerber@suse.de, rth@twiddle.net On Thu, May 28, 2015 at 03:37:03PM +1000, Alistair Francis wrote: > Move the Microblaze PVR registers to the end of the CPUMBState > and preserve them during reset. This is similar to what the > QEMU ARM model does with some of it's registers. > > This allows the Microblaze PVR registers to only be set once > at realise instead of constantly at reset. > > Signed-off-by: Alistair Francis > Reviewed-by: Peter Crosthwaite Reviewed-by: Edgar E. Iglesias > --- > V2: > - Remove the memset and cpu_reset functions as they aren't > required in the realize and I'm touching them anyway. > > NOTE: The individual machine resets still write to the PVR > registers on each reset. This is no longer required as it only > needs to be done once. Instead of moving them now, they are > being left there and will be removed when they are all > converted to the standard CPU properties. > > target-microblaze/cpu.c | 40 ++++++++++++++++++++++------------------ > target-microblaze/cpu.h | 10 ++++++---- > 2 files changed, 28 insertions(+), 22 deletions(-) > > diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c > index 67e3182..95be540 100644 > --- a/target-microblaze/cpu.c > +++ b/target-microblaze/cpu.c > @@ -63,13 +63,34 @@ static void mb_cpu_reset(CPUState *s) > > mcc->parent_reset(s); > > - memset(env, 0, sizeof(CPUMBState)); > + memset(env, 0, offsetof(CPUMBState, pvr)); > env->res_addr = RES_ADDR_NONE; > tlb_flush(s, 1); > > /* Disable stack protector. */ > env->shr = ~0; > > +#if defined(CONFIG_USER_ONLY) > + /* start in user mode with interrupts enabled. */ > + env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; > +#else > + env->sregs[SR_MSR] = 0; > + mmu_init(&env->mmu); > + env->mmu.c_mmu = 3; > + env->mmu.c_mmu_tlb_access = 3; > + env->mmu.c_mmu_zones = 16; > +#endif > +} > + > +static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > +{ > + CPUState *cs = CPU(dev); > + MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); > + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); > + CPUMBState *env = &cpu->env; > + > + qemu_init_vcpu(cs); > + > env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ > | PVR0_USE_BARREL_MASK \ > | PVR0_USE_DIV_MASK \ > @@ -99,25 +120,8 @@ static void mb_cpu_reset(CPUState *s) > env->sregs[SR_PC] = cpu->base_vectors; > > #if defined(CONFIG_USER_ONLY) > - /* start in user mode with interrupts enabled. */ > - env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; > env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ > -#else > - env->sregs[SR_MSR] = 0; > - mmu_init(&env->mmu); > - env->mmu.c_mmu = 3; > - env->mmu.c_mmu_tlb_access = 3; > - env->mmu.c_mmu_zones = 16; > #endif > -} > - > -static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > -{ > - CPUState *cs = CPU(dev); > - MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); > - > - cpu_reset(cs); > - qemu_init_vcpu(cs); > > mcc->parent_realize(dev, errp); > } > diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h > index 4ea04ac..e4c1cde 100644 > --- a/target-microblaze/cpu.h > +++ b/target-microblaze/cpu.h > @@ -260,16 +260,18 @@ struct CPUMBState { > #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) > uint32_t iflags; > > - struct { > - uint32_t regs[16]; > - } pvr; > - > #if !defined(CONFIG_USER_ONLY) > /* Unified MMU. */ > struct microblaze_mmu mmu; > #endif > > CPU_COMMON > + > + /* These fields are preserved on reset. */ > + > + struct { > + uint32_t regs[16]; > + } pvr; > }; > > #include "cpu-qom.h" > -- > 1.7.1 >