[Qemu-devel] [PATCH 0/7] Add system_powerdown support on ARM through ACPI and DT

[Qemu-devel] [PATCH 0/7] Add system_powerdown support on ARM through ACPI and DT

[shannon.zhao]

From: Shannon Zhao <shannon.zhao@linaro.org>

ACPI SPEC 5.0 defines GPIO-signaled ACPI Events for Hardware-reduced
platforms(like ARM). It uses GPIO pin to trigger an event to the guest.
For QEMU, here we add PL061 GPIO controller and use PIN 3 for
system_powerdown, reserving PIN 0, 1, 2 for PCI hotplug, CPU hotplug and
memory hotplug.

This patchset adds system_powerdown support on ARM through both ACPI and
DT ways. It adds a GPIO controller(here is PL061) in machine virt and
uses GPIO-singled event for ACPI while gpio-keys for DT. It can be
fetched from [1] and has been tested for the guests starting by ACPI or
DT while guests use systemd or acpid.

a) ACPI way. As ACPI on ARM64 doesn't support probing amba device, we
should convert the PL061 to platform device(apply patch[2]). In addition,
we should use ACPI to start VM, referring to below script. QEMU_EFI.fd
can be fetched from [3]. 
Note: The guest kernel must have the ARM64 ACPI support(the related
patches are in upstream kernel now) and uart SBSA support for ACPI [4].

    qemu-system-aarch64 \
    -smp 1 -m 1024 -M virt \
    -cpu cortex-a57 -nographic \
    -monitor telnet::4444,server,nowait \
    -bios QEMU_EFI.fd \
    -kernel Image \
    -initrd guestfs.cpio.gz \
    -append "rdinit=/sbin/init console=ttySBSA mem=512M root=/dev/ram earlycon=pl011,0x9000000 rw acpi=force"

b) DT way. Apply patch[2] as well. Start vm as usual.

    qemu-system-aarch64 \
    -smp 1 -m 1024 -M virt \
    -cpu cortex-a57 -nographic \
    -monitor telnet::4444,server,nowait \
    -kernel Image \
    -initrd guestfs.cpio.gz \
    -append "rdinit=/sbin/init console=ttyAMA0 mem=512M root=/dev/ram earlycon=pl011,0x9000000 rw"

Guest internal setup:
If your guest FS uses systemd, you should check file
/lib/udev/rules.d/70-power-switch.rules and add the following line in it
if it doesn't exist.

SUBSYSTEM=="input", KERNEL=="event*", SUBSYSTEMS=="platform",
ATTRS{keys}=="116", TAG+="power-switch"

If your guest FS uses acpid, you should check it has
/etc/acpi/powerbtn.sh and /etc/acpi/events/powerbtn. Refer to [5] for
the setup of acpid.

Thanks,
Shannon

[1] https://git.linaro.org/people/shannon.zhao/qemu.git/shortlog/refs/heads/PowerButton
[2] http://people.linaro.org/~shannon.zhao/PowerButton/0001-PL061-convert-to-platform-device.patch
[3] http://people.linaro.org/~shannon.zhao/ACPI_ARM/QEMU_EFI.fd
[4] http://people.linaro.org/~shannon.zhao/ACPI_ARM/0001-tty-SBSA-compatible-UART.patch
[5] https://wiki.linaro.org/LEG/Engineering/Kernel/ACPI/GPIOPowerButton

Shannon Zhao (7):
  hw/arm/virt: Add a GPIO controller
  hw/arm/virt-acpi-build: Add GPIO controller in ACPI DSDT table
  hw/arm/virt-acpi-build: Add power button device in ACPI DSDT table
  hw/acpi/aml-build: Add aml_gpio_int() term
  hw/arm/virt-acpi-build: Add _E03 for Power Button
  hw/arm/virt: Add QEMU powerdown notifier and hook it to GPIO Pin 3
  hw/arm/virt: Add gpio-keys node for Poweroff using DT

 hw/acpi/aml-build.c         | 60 +++++++++++++++++++++++++++++++++++++++++++++
 hw/arm/virt-acpi-build.c    | 43 ++++++++++++++++++++++++++++++++
 hw/arm/virt.c               | 60 +++++++++++++++++++++++++++++++++++++++++++++
 include/hw/acpi/aml-build.h | 16 ++++++++++++
 include/hw/arm/virt.h       |  1 +
 5 files changed, 180 insertions(+)

-- 
2.1.0

[Qemu-devel] [PATCH 1/7] hw/arm/virt: Add a GPIO controller

[shannon.zhao]

From: Shannon Zhao <shannon.zhao@linaro.org>

ACPI 5.0 supports GPIO-signaled ACPI Events. This can be used for
powerdown, hotplug evnets. Add a GPIO controller in machine virt,
to support powerdown, maybe can be used for cpu hotplug. And
here we use pl061.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 hw/arm/virt.c         | 30 ++++++++++++++++++++++++++++++
 include/hw/arm/virt.h |  1 +
 2 files changed, 31 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 3951326..3511903 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -111,6 +111,7 @@ static const MemMapEntry a15memmap[] = {
     [VIRT_UART] =       { 0x09000000, 0x00001000 },
     [VIRT_RTC] =        { 0x09010000, 0x00001000 },
     [VIRT_FW_CFG] =     { 0x09020000, 0x0000000a },
+    [VIRT_GPIO] =       { 0x09030000, 0x00001000 },
     [VIRT_MMIO] =       { 0x0a000000, 0x00000200 },
     /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
     /*
@@ -128,6 +129,7 @@ static const int a15irqmap[] = {
     [VIRT_UART] = 1,
     [VIRT_RTC] = 2,
     [VIRT_PCIE] = 3, /* ... to 6 */
+    [VIRT_GPIO] = 7,
     [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
 };
 
@@ -430,6 +432,32 @@ static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic)
     g_free(nodename);
 }
 
+static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic)
+{
+    char *nodename;
+    hwaddr base = vbi->memmap[VIRT_GPIO].base;
+    hwaddr size = vbi->memmap[VIRT_GPIO].size;
+    int irq = vbi->irqmap[VIRT_GPIO];
+    const char compat[] = "arm,pl061";
+
+    sysbus_create_simple("pl061", base, pic[irq]);
+
+    nodename = g_strdup_printf("/pl061@%" PRIx64, base);
+    qemu_fdt_add_subnode(vbi->fdt, nodename);
+    qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
+                                 2, base, 2, size);
+    qemu_fdt_setprop(vbi->fdt, nodename, "compatible", compat, sizeof(compat));
+    qemu_fdt_setprop_cell(vbi->fdt, nodename, "#gpio-cells", 2);
+    qemu_fdt_setprop(vbi->fdt, nodename, "gpio-controller", NULL, 0);
+    qemu_fdt_setprop_cells(vbi->fdt, nodename, "interrupts",
+                           GIC_FDT_IRQ_TYPE_SPI, irq,
+                           GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+    qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle);
+    qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk");
+
+    g_free(nodename);
+}
+
 static void create_virtio_devices(const VirtBoardInfo *vbi, qemu_irq *pic)
 {
     int i;
@@ -821,6 +849,8 @@ static void machvirt_init(MachineState *machine)
 
     create_rtc(vbi, pic);
 
+    create_gpio(vbi, pic);
+
     guest_info->pcie_info = create_pcie(vbi, pic, gic_phandle);
 
     /* Create mmio transports, so the user can create virtio backends
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index ba7fe0b..31b7eba 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -50,6 +50,7 @@ enum {
     VIRT_RTC,
     VIRT_FW_CFG,
     VIRT_PCIE,
+    VIRT_GPIO,
 };
 
 typedef struct MemMapEntry {
-- 
2.1.0

[Qemu-devel] [PATCH 2/7] hw/arm/virt-acpi-build: Add GPIO controller in ACPI DSDT table

[shannon.zhao]

From: Shannon Zhao <shannon.zhao@linaro.org>

Add GPIO controller in ACPI DSDT table. It can be used
for gpio event.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 hw/arm/virt-acpi-build.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index b3f27d0..e505c16 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -301,6 +301,24 @@ static void acpi_dsdt_add_pci(Aml *scope, VirtAcpiPcieInfo *info, int pcie_irq)
     aml_append(scope, dev);
 }
 
+static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
+                                           int gpio_irq)
+{
+    Aml *dev = aml_device("GPO0");
+    aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0009")));
+    aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+
+    Aml *crs = aml_resource_template();
+    aml_append(crs, aml_memory32_fixed(gpio_memmap->base,
+                                       gpio_memmap->size, aml_ReadWrite));
+    aml_append(crs,
+               aml_interrupt(aml_consumer, aml_edge, aml_active_high,
+               aml_exclusive, aml_not_wake_capable, gpio_irq + 32));
+    aml_append(dev, aml_name_decl("_CRS", crs));
+    aml_append(scope, dev);
+}
+
 /* RSDP */
 static GArray *
 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
@@ -456,6 +474,7 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
     acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
                                 irqmap[VIRT_MMIO], NUM_VIRTIO_TRANSPORTS);
     acpi_dsdt_add_pci(scope, guest_info->pcie_info, irqmap[VIRT_PCIE]);
+    acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], irqmap[VIRT_GPIO]);
 
     aml_append(dsdt, scope);
 
-- 
2.1.0

[Qemu-devel] [PATCH 3/7] hw/arm/virt-acpi-build: Add power button device in ACPI DSDT table

[shannon.zhao]

From: Shannon Zhao <shannon.zhao@linaro.org>

Add power button device in ACPI DSDT table.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 hw/arm/virt-acpi-build.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index e505c16..b582047 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -319,6 +319,18 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
     aml_append(scope, dev);
 }
 
+static void acpi_dsdt_add_power_button(Aml *scope)
+{
+    Aml *dev = aml_device("PWRB");
+    aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C0C")));
+    aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
+    aml_append(dev, aml_name_decl("_UID", aml_int(0)));
+    Aml *method = aml_method("_STA", 0);
+    aml_append(method, aml_return(aml_int(0x0F)));
+    aml_append(dev, method);
+    aml_append(scope, dev);
+}
+
 /* RSDP */
 static GArray *
 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
@@ -475,6 +487,7 @@ build_dsdt(GArray *table_data, GArray *linker, VirtGuestInfo *guest_info)
                                 irqmap[VIRT_MMIO], NUM_VIRTIO_TRANSPORTS);
     acpi_dsdt_add_pci(scope, guest_info->pcie_info, irqmap[VIRT_PCIE]);
     acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO], irqmap[VIRT_GPIO]);
+    acpi_dsdt_add_power_button(scope);
 
     aml_append(dsdt, scope);
 
-- 
2.1.0

[Qemu-devel] [PATCH 4/7] hw/acpi/aml-build: Add aml_gpio_int() term

[shannon.zhao]

From: Shannon Zhao <shannon.zhao@linaro.org>

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 hw/acpi/aml-build.c         | 60 +++++++++++++++++++++++++++++++++++++++++++++
 include/hw/acpi/aml-build.h | 16 ++++++++++++
 2 files changed, 76 insertions(+)

diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
index 643e885..40d7fa0 100644
--- a/hw/acpi/aml-build.c
+++ b/hw/acpi/aml-build.c
@@ -525,6 +525,66 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
 }
 
 /*
+ * ACPI 5.0: 19.5.53
+ * GpioInt(GPIO Interrupt Connection Resource Descriptor Macro)
+ */
+Aml *aml_gpio_int(AmlLevelAndEdge level_and_edge,
+                  AmlActiveHighAndLow high_and_low,
+                  AmlExclusiveAndShared exclusive_and_shared,
+                  AmlWakeCap wake_capable, AmlPinConfig pin_cfg,
+                  int32_t pin_num, const char *name)
+{
+    Aml *var = aml_alloc();
+    uint8_t flags = level_and_edge | (high_and_low << 1)
+                    | (exclusive_and_shared << 3) | (wake_capable << 4);
+
+    build_append_byte(var->buf, 0x8C); /* GpioInt Resource Descriptor */
+    /* Length */
+    build_append_byte(var->buf, 0x1B); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+    build_append_byte(var->buf, 1); /* Revision ID */
+    /* GPIO Connection Type 0x00 = Interrupt Connection */
+    build_append_byte(var->buf, 0);
+    /* General Flags */
+    build_append_byte(var->buf, 1); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+    /* Interrupt and IO Flags */
+    build_append_byte(var->buf, flags); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+    /* Pin Configuration 0 = Default 1 = Pull-up 2 = Pull-down 3 = No Pull */
+    build_append_byte(var->buf, pin_cfg);
+    /* Output Drive Strength */
+    build_append_byte(var->buf, 0); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+    /* Debounce timeout */
+    build_append_byte(var->buf, 0); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+
+    /* Pin Table Offset */
+    build_append_byte(var->buf, 0x17); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+    /* Resource Source Index */
+    build_append_byte(var->buf, 0);
+    /* Resource Source Name */
+    build_append_byte(var->buf, 0x19); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+    /* Vendor Data Offse */
+    build_append_byte(var->buf, 0x1E); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+    /* Vendor Data Length */
+    build_append_byte(var->buf, 0); /* bits[7:0] */
+    build_append_byte(var->buf, 0); /* bits[15:8] */
+    /* Pin Numbe */
+    build_append_byte(var->buf, pin_num & 0xff); /* bits[7:0] */
+    build_append_byte(var->buf, (pin_num >> 8) & 0xff); /* bits[15:8] */
+    /* Resource Source */
+    build_append_namestring(var->buf, "%s", name);
+    build_append_byte(var->buf, '\0');
+
+    return var;
+}
+
+/*
  * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
  */
 Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
index 39b44e4..b95a8e8 100644
--- a/include/hw/acpi/aml-build.h
+++ b/include/hw/acpi/aml-build.h
@@ -150,6 +150,17 @@ typedef enum {
     aml_wake_capable = 1,
 } AmlWakeCap;
 
+/*
+ * ACPI 5.0: Table 6-189 GPIO Connection Descriptor Definition
+ * _PPI field definition
+ */
+typedef enum {
+    aml_default_config = 0,
+    aml_pull_up = 1,
+    aml_pull_down = 2,
+    aml_no_pull = 3,
+} AmlPinConfig;
+
 typedef
 struct AcpiBuildTables {
     GArray *table_data;
@@ -208,6 +219,11 @@ Aml *aml_call1(const char *method, Aml *arg1);
 Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
 Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
 Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
+Aml *aml_gpio_int(AmlLevelAndEdge level_and_edge,
+                  AmlActiveHighAndLow high_and_low,
+                  AmlExclusiveAndShared exclusive_and_shared,
+                  AmlWakeCap wake_capable, AmlPinConfig pin_cfg,
+                  int32_t pin_num, const char *name);
 Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
                         AmlReadAndWrite read_and_write);
 Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
-- 
2.1.0

Re: [Qemu-devel] [PATCH 4/7] hw/acpi/aml-build: Add aml_gpio_int() term

[Michael S. Tsirkin]

On Tue, May 12, 2015 at 12:24:13PM +0800, shannon.zhao@linaro.org wrote:
> From: Shannon Zhao <shannon.zhao@linaro.org>
> 
> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> ---
>  hw/acpi/aml-build.c         | 60 +++++++++++++++++++++++++++++++++++++++++++++
>  include/hw/acpi/aml-build.h | 16 ++++++++++++
>  2 files changed, 76 insertions(+)
> 
> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> index 643e885..40d7fa0 100644
> --- a/hw/acpi/aml-build.c
> +++ b/hw/acpi/aml-build.c
> @@ -525,6 +525,66 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
>  }
>  
>  /*
> + * ACPI 5.0: 19.5.53
> + * GpioInt(GPIO Interrupt Connection Resource Descriptor Macro)

GpioInt is an ASL thing, it has no place in QEMU as we
don't use ASL.

What you should point at, and model API after, is
6.4.3.8.1 GPIO Connection Descriptor

In fact, why not describe the layout with a struct?

That's much nicer than building it up byte by byte.
Also, this way offsets will be self-documenting
using sizeof.

> + */
> +Aml *aml_gpio_int(AmlLevelAndEdge level_and_edge,
> +                  AmlActiveHighAndLow high_and_low,
> +                  AmlExclusiveAndShared exclusive_and_shared,
> +                  AmlWakeCap wake_capable, AmlPinConfig pin_cfg,
> +                  int32_t pin_num, const char *name)
> +{
> +    Aml *var = aml_alloc();
> +    uint8_t flags = level_and_edge | (high_and_low << 1)
> +                    | (exclusive_and_shared << 3) | (wake_capable << 4);
> +
> +    build_append_byte(var->buf, 0x8C); /* GpioInt Resource Descriptor */
> +    /* Length */
> +    build_append_byte(var->buf, 0x1B); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +    build_append_byte(var->buf, 1); /* Revision ID */
> +    /* GPIO Connection Type 0x00 = Interrupt Connection */
> +    build_append_byte(var->buf, 0);
> +    /* General Flags */
> +    build_append_byte(var->buf, 1); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +    /* Interrupt and IO Flags */
> +    build_append_byte(var->buf, flags); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +    /* Pin Configuration 0 = Default 1 = Pull-up 2 = Pull-down 3 = No Pull */
> +    build_append_byte(var->buf, pin_cfg);
> +    /* Output Drive Strength */
> +    build_append_byte(var->buf, 0); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +    /* Debounce timeout */
> +    build_append_byte(var->buf, 0); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +
> +    /* Pin Table Offset */
> +    build_append_byte(var->buf, 0x17); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +    /* Resource Source Index */
> +    build_append_byte(var->buf, 0);
> +    /* Resource Source Name */
> +    build_append_byte(var->buf, 0x19); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +    /* Vendor Data Offse */

Offset?

> +    build_append_byte(var->buf, 0x1E); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +    /* Vendor Data Length */
> +    build_append_byte(var->buf, 0); /* bits[7:0] */
> +    build_append_byte(var->buf, 0); /* bits[15:8] */
> +    /* Pin Numbe */

Number?

> +    build_append_byte(var->buf, pin_num & 0xff); /* bits[7:0] */
> +    build_append_byte(var->buf, (pin_num >> 8) & 0xff); /* bits[15:8] */
> +    /* Resource Source */
> +    build_append_namestring(var->buf, "%s", name);
> +    build_append_byte(var->buf, '\0');
> +
> +    return var;
> +}
> +
> +/*
>   * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
>   */
>  Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> index 39b44e4..b95a8e8 100644
> --- a/include/hw/acpi/aml-build.h
> +++ b/include/hw/acpi/aml-build.h
> @@ -150,6 +150,17 @@ typedef enum {
>      aml_wake_capable = 1,
>  } AmlWakeCap;
>  
> +/*
> + * ACPI 5.0: Table 6-189 GPIO Connection Descriptor Definition
> + * _PPI field definition
> + */
> +typedef enum {
> +    aml_default_config = 0,
> +    aml_pull_up = 1,
> +    aml_pull_down = 2,
> +    aml_no_pull = 3,
> +} AmlPinConfig;
> +
>  typedef
>  struct AcpiBuildTables {
>      GArray *table_data;
> @@ -208,6 +219,11 @@ Aml *aml_call1(const char *method, Aml *arg1);
>  Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
>  Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
>  Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
> +Aml *aml_gpio_int(AmlLevelAndEdge level_and_edge,
> +                  AmlActiveHighAndLow high_and_low,
> +                  AmlExclusiveAndShared exclusive_and_shared,
> +                  AmlWakeCap wake_capable, AmlPinConfig pin_cfg,
> +                  int32_t pin_num, const char *name);
>  Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
>                          AmlReadAndWrite read_and_write);
>  Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
> -- 
> 2.1.0
> 

Re: [Qemu-devel] [PATCH 4/7] hw/acpi/aml-build: Add aml_gpio_int() term

[Michael S. Tsirkin]

On Sun, May 31, 2015 at 08:13:37PM +0200, Michael S. Tsirkin wrote:
> On Tue, May 12, 2015 at 12:24:13PM +0800, shannon.zhao@linaro.org wrote:
> > From: Shannon Zhao <shannon.zhao@linaro.org>
> > 
> > Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> > ---
> >  hw/acpi/aml-build.c         | 60 +++++++++++++++++++++++++++++++++++++++++++++
> >  include/hw/acpi/aml-build.h | 16 ++++++++++++
> >  2 files changed, 76 insertions(+)
> > 
> > diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
> > index 643e885..40d7fa0 100644
> > --- a/hw/acpi/aml-build.c
> > +++ b/hw/acpi/aml-build.c
> > @@ -525,6 +525,66 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
> >  }
> >  
> >  /*
> > + * ACPI 5.0: 19.5.53
> > + * GpioInt(GPIO Interrupt Connection Resource Descriptor Macro)
> 
> GpioInt is an ASL thing, it has no place in QEMU as we
> don't use ASL.
> 
> What you should point at, and model API after, is
> 6.4.3.8.1 GPIO Connection Descriptor

You can make a wrapper for GpioInt if you like, but
it should be layered on top of GPIO Connection Descriptor.


> In fact, why not describe the layout with a struct?
> 
> That's much nicer than building it up byte by byte.
> Also, this way offsets will be self-documenting
> using sizeof.

Or at least, use build_append_int_noprefix for multibyte fields.

> > + */
> > +Aml *aml_gpio_int(AmlLevelAndEdge level_and_edge,
> > +                  AmlActiveHighAndLow high_and_low,
> > +                  AmlExclusiveAndShared exclusive_and_shared,
> > +                  AmlWakeCap wake_capable, AmlPinConfig pin_cfg,
> > +                  int32_t pin_num, const char *name)
> > +{
> > +    Aml *var = aml_alloc();
> > +    uint8_t flags = level_and_edge | (high_and_low << 1)
> > +                    | (exclusive_and_shared << 3) | (wake_capable << 4);
> > +
> > +    build_append_byte(var->buf, 0x8C); /* GpioInt Resource Descriptor */
> > +    /* Length */
> > +    build_append_byte(var->buf, 0x1B); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +    build_append_byte(var->buf, 1); /* Revision ID */
> > +    /* GPIO Connection Type 0x00 = Interrupt Connection */
> > +    build_append_byte(var->buf, 0);
> > +    /* General Flags */
> > +    build_append_byte(var->buf, 1); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +    /* Interrupt and IO Flags */
> > +    build_append_byte(var->buf, flags); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +    /* Pin Configuration 0 = Default 1 = Pull-up 2 = Pull-down 3 = No Pull */
> > +    build_append_byte(var->buf, pin_cfg);
> > +    /* Output Drive Strength */
> > +    build_append_byte(var->buf, 0); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +    /* Debounce timeout */
> > +    build_append_byte(var->buf, 0); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +
> > +    /* Pin Table Offset */
> > +    build_append_byte(var->buf, 0x17); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +    /* Resource Source Index */
> > +    build_append_byte(var->buf, 0);
> > +    /* Resource Source Name */
> > +    build_append_byte(var->buf, 0x19); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +    /* Vendor Data Offse */
> 
> Offset?
> 
> > +    build_append_byte(var->buf, 0x1E); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +    /* Vendor Data Length */
> > +    build_append_byte(var->buf, 0); /* bits[7:0] */
> > +    build_append_byte(var->buf, 0); /* bits[15:8] */
> > +    /* Pin Numbe */
> 
> Number?
> 
> > +    build_append_byte(var->buf, pin_num & 0xff); /* bits[7:0] */
> > +    build_append_byte(var->buf, (pin_num >> 8) & 0xff); /* bits[15:8] */
> > +    /* Resource Source */
> > +    build_append_namestring(var->buf, "%s", name);
> > +    build_append_byte(var->buf, '\0');
> > +
> > +    return var;
> > +}
> > +
> > +/*
> >   * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
> >   */
> >  Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
> > diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
> > index 39b44e4..b95a8e8 100644
> > --- a/include/hw/acpi/aml-build.h
> > +++ b/include/hw/acpi/aml-build.h
> > @@ -150,6 +150,17 @@ typedef enum {
> >      aml_wake_capable = 1,
> >  } AmlWakeCap;
> >  
> > +/*
> > + * ACPI 5.0: Table 6-189 GPIO Connection Descriptor Definition
> > + * _PPI field definition
> > + */
> > +typedef enum {
> > +    aml_default_config = 0,
> > +    aml_pull_up = 1,
> > +    aml_pull_down = 2,
> > +    aml_no_pull = 3,
> > +} AmlPinConfig;
> > +
> >  typedef
> >  struct AcpiBuildTables {
> >      GArray *table_data;
> > @@ -208,6 +219,11 @@ Aml *aml_call1(const char *method, Aml *arg1);
> >  Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
> >  Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
> >  Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
> > +Aml *aml_gpio_int(AmlLevelAndEdge level_and_edge,
> > +                  AmlActiveHighAndLow high_and_low,
> > +                  AmlExclusiveAndShared exclusive_and_shared,
> > +                  AmlWakeCap wake_capable, AmlPinConfig pin_cfg,
> > +                  int32_t pin_num, const char *name);
> >  Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
> >                          AmlReadAndWrite read_and_write);
> >  Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
> > -- 
> > 2.1.0
> > 

Re: [Qemu-devel] [PATCH 4/7] hw/acpi/aml-build: Add aml_gpio_int() term

[Shannon Zhao]

On 2015/6/1 2:21, Michael S. Tsirkin wrote:
> On Sun, May 31, 2015 at 08:13:37PM +0200, Michael S. Tsirkin wrote:
>> On Tue, May 12, 2015 at 12:24:13PM +0800, shannon.zhao@linaro.org wrote:
>>> From: Shannon Zhao <shannon.zhao@linaro.org>
>>>
>>> Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
>>> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>>> ---
>>>  hw/acpi/aml-build.c         | 60 +++++++++++++++++++++++++++++++++++++++++++++
>>>  include/hw/acpi/aml-build.h | 16 ++++++++++++
>>>  2 files changed, 76 insertions(+)
>>>
>>> diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c
>>> index 643e885..40d7fa0 100644
>>> --- a/hw/acpi/aml-build.c
>>> +++ b/hw/acpi/aml-build.c
>>> @@ -525,6 +525,66 @@ Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4)
>>>  }
>>>  
>>>  /*
>>> + * ACPI 5.0: 19.5.53
>>> + * GpioInt(GPIO Interrupt Connection Resource Descriptor Macro)
>>
>> GpioInt is an ASL thing, it has no place in QEMU as we
>> don't use ASL.
>>
>> What you should point at, and model API after, is
>> 6.4.3.8.1 GPIO Connection Descriptor
> 
> You can make a wrapper for GpioInt if you like, but
> it should be layered on top of GPIO Connection Descriptor.
> 
Ok, I see. Thanks.

> 
>> In fact, why not describe the layout with a struct?
>>
>> That's much nicer than building it up byte by byte.
>> Also, this way offsets will be self-documenting
>> using sizeof.
> 
> Or at least, use build_append_int_noprefix for multibyte fields.
> 
>>> + */
>>> +Aml *aml_gpio_int(AmlLevelAndEdge level_and_edge,
>>> +                  AmlActiveHighAndLow high_and_low,
>>> +                  AmlExclusiveAndShared exclusive_and_shared,
>>> +                  AmlWakeCap wake_capable, AmlPinConfig pin_cfg,
>>> +                  int32_t pin_num, const char *name)
>>> +{
>>> +    Aml *var = aml_alloc();
>>> +    uint8_t flags = level_and_edge | (high_and_low << 1)
>>> +                    | (exclusive_and_shared << 3) | (wake_capable << 4);
>>> +
>>> +    build_append_byte(var->buf, 0x8C); /* GpioInt Resource Descriptor */
>>> +    /* Length */
>>> +    build_append_byte(var->buf, 0x1B); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +    build_append_byte(var->buf, 1); /* Revision ID */
>>> +    /* GPIO Connection Type 0x00 = Interrupt Connection */
>>> +    build_append_byte(var->buf, 0);
>>> +    /* General Flags */
>>> +    build_append_byte(var->buf, 1); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +    /* Interrupt and IO Flags */
>>> +    build_append_byte(var->buf, flags); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +    /* Pin Configuration 0 = Default 1 = Pull-up 2 = Pull-down 3 = No Pull */
>>> +    build_append_byte(var->buf, pin_cfg);
>>> +    /* Output Drive Strength */
>>> +    build_append_byte(var->buf, 0); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +    /* Debounce timeout */
>>> +    build_append_byte(var->buf, 0); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +
>>> +    /* Pin Table Offset */
>>> +    build_append_byte(var->buf, 0x17); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +    /* Resource Source Index */
>>> +    build_append_byte(var->buf, 0);
>>> +    /* Resource Source Name */
>>> +    build_append_byte(var->buf, 0x19); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +    /* Vendor Data Offse */
>>
>> Offset?
>>
>>> +    build_append_byte(var->buf, 0x1E); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +    /* Vendor Data Length */
>>> +    build_append_byte(var->buf, 0); /* bits[7:0] */
>>> +    build_append_byte(var->buf, 0); /* bits[15:8] */
>>> +    /* Pin Numbe */
>>
>> Number?
>>
>>> +    build_append_byte(var->buf, pin_num & 0xff); /* bits[7:0] */
>>> +    build_append_byte(var->buf, (pin_num >> 8) & 0xff); /* bits[15:8] */
>>> +    /* Resource Source */
>>> +    build_append_namestring(var->buf, "%s", name);
>>> +    build_append_byte(var->buf, '\0');
>>> +
>>> +    return var;
>>> +}
>>> +
>>> +/*
>>>   * ACPI 1.0: 6.4.3.4 Memory32Fixed (Memory Resource Descriptor Macro)
>>>   */
>>>  Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
>>> diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h
>>> index 39b44e4..b95a8e8 100644
>>> --- a/include/hw/acpi/aml-build.h
>>> +++ b/include/hw/acpi/aml-build.h
>>> @@ -150,6 +150,17 @@ typedef enum {
>>>      aml_wake_capable = 1,
>>>  } AmlWakeCap;
>>>  
>>> +/*
>>> + * ACPI 5.0: Table 6-189 GPIO Connection Descriptor Definition
>>> + * _PPI field definition
>>> + */
>>> +typedef enum {
>>> +    aml_default_config = 0,
>>> +    aml_pull_up = 1,
>>> +    aml_pull_down = 2,
>>> +    aml_no_pull = 3,
>>> +} AmlPinConfig;
>>> +
>>>  typedef
>>>  struct AcpiBuildTables {
>>>      GArray *table_data;
>>> @@ -208,6 +219,11 @@ Aml *aml_call1(const char *method, Aml *arg1);
>>>  Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2);
>>>  Aml *aml_call3(const char *method, Aml *arg1, Aml *arg2, Aml *arg3);
>>>  Aml *aml_call4(const char *method, Aml *arg1, Aml *arg2, Aml *arg3, Aml *arg4);
>>> +Aml *aml_gpio_int(AmlLevelAndEdge level_and_edge,
>>> +                  AmlActiveHighAndLow high_and_low,
>>> +                  AmlExclusiveAndShared exclusive_and_shared,
>>> +                  AmlWakeCap wake_capable, AmlPinConfig pin_cfg,
>>> +                  int32_t pin_num, const char *name);
>>>  Aml *aml_memory32_fixed(uint32_t addr, uint32_t size,
>>>                          AmlReadAndWrite read_and_write);
>>>  Aml *aml_interrupt(AmlConsumerAndProducer con_and_pro,
>>> -- 
>>> 2.1.0
>>>
> 
> .
> 

-- 
Shannon

[Qemu-devel] [PATCH 5/7] hw/arm/virt-acpi-build: Add _E03 for Power Button

[shannon.zhao]

From: Shannon Zhao <shannon.zhao@linaro.org>

Here GPIO pin 3 is used for Power Button, add _E03 in ACPI DSDT table.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 hw/arm/virt-acpi-build.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index b582047..1fcdd74 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -316,6 +316,17 @@ static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
                aml_interrupt(aml_consumer, aml_edge, aml_active_high,
                aml_exclusive, aml_not_wake_capable, gpio_irq + 32));
     aml_append(dev, aml_name_decl("_CRS", crs));
+
+    Aml *aei = aml_resource_template();
+    /* Pin 3 for power button */
+    aml_append(aei, aml_gpio_int(aml_edge, aml_active_high, aml_exclusive,
+                         aml_wake_capable, aml_pull_up, 3, "GPO0"));
+    aml_append(dev, aml_name_decl("_AEI", aei));
+
+    /* _E03 is handle for power button */
+    Aml *method = aml_method("_E03", 0);
+    aml_append(method, aml_notify(aml_name("PWRB"), aml_int(0x80)));
+    aml_append(dev, method);
     aml_append(scope, dev);
 }
 
-- 
2.1.0

[Qemu-devel] [PATCH 6/7] hw/arm/virt: Add QEMU powerdown notifier and hook it to GPIO Pin 3

[shannon.zhao]

From: Shannon Zhao <shannon.zhao@linaro.org>

Currently mach-virt model doesn't support powerdown request. Guest VM
doesn't react to system_powerdown from monitor console (or QMP) because
there is no communication mechanism for such requests. This patch registers
GPIO Pin 3 with powerdown notification. So guest VM can receive notification
when such powerdown request is triggered.

Signed-off-by: Wei Huang <wei@redhat.com>
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 hw/arm/virt.c | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 3511903..354b020 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -432,6 +432,18 @@ static void create_rtc(const VirtBoardInfo *vbi, qemu_irq *pic)
     g_free(nodename);
 }
 
+static DeviceState *pl061_dev;
+static void virt_powerdown_req(Notifier *n, void *opaque)
+{
+    /* use gpio Pin 3 for power button event */
+    qemu_set_irq(qdev_get_gpio_in(pl061_dev, 3), 0);
+    qemu_set_irq(qdev_get_gpio_in(pl061_dev, 3), 1);
+}
+
+static Notifier virt_system_powerdown_notifier = {
+    .notify = virt_powerdown_req
+};
+
 static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic)
 {
     char *nodename;
@@ -440,7 +452,7 @@ static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic)
     int irq = vbi->irqmap[VIRT_GPIO];
     const char compat[] = "arm,pl061";
 
-    sysbus_create_simple("pl061", base, pic[irq]);
+    pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
 
     nodename = g_strdup_printf("/pl061@%" PRIx64, base);
     qemu_fdt_add_subnode(vbi->fdt, nodename);
@@ -455,6 +467,9 @@ static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic)
     qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle);
     qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk");
 
+    /* connect powerdown request */
+    qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
+
     g_free(nodename);
 }
 
-- 
2.1.0

[Qemu-devel] [PATCH 7/7] hw/arm/virt: Add gpio-keys node for Poweroff using DT

[shannon.zhao]

From: Shannon Zhao <shannon.zhao@linaro.org>

Add a gpio-keys node. This is used for Poweroff for the systems which
use DT not ACPI.

Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
---
 hw/arm/virt.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 354b020..a6f39c0 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -454,6 +454,7 @@ static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic)
 
     pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
 
+    uint32_t phandle = qemu_fdt_alloc_phandle(vbi->fdt);
     nodename = g_strdup_printf("/pl061@%" PRIx64, base);
     qemu_fdt_add_subnode(vbi->fdt, nodename);
     qemu_fdt_setprop_sized_cells(vbi->fdt, nodename, "reg",
@@ -466,6 +467,20 @@ static void create_gpio(const VirtBoardInfo *vbi, qemu_irq *pic)
                            GIC_FDT_IRQ_FLAGS_LEVEL_HI);
     qemu_fdt_setprop_cell(vbi->fdt, nodename, "clocks", vbi->clock_phandle);
     qemu_fdt_setprop_string(vbi->fdt, nodename, "clock-names", "apb_pclk");
+    qemu_fdt_setprop_cell(vbi->fdt, nodename, "phandle", phandle);
+
+    qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys");
+    qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys", "compatible", "gpio-keys");
+    qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#size-cells", 0);
+    qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys", "#address-cells", 1);
+    qemu_fdt_setprop(vbi->fdt, "/gpio-keys", "autorepeat", NULL, 0);
+
+    qemu_fdt_add_subnode(vbi->fdt, "/gpio-keys/poweroff");
+    qemu_fdt_setprop_string(vbi->fdt, "/gpio-keys/poweroff",
+                            "label", "GPIO Key Poweroff");
+    qemu_fdt_setprop_cell(vbi->fdt, "/gpio-keys/poweroff", "linux,code", 116);
+    qemu_fdt_setprop_cells(vbi->fdt, "/gpio-keys/poweroff",
+                           "gpios", phandle, 3, 0);
 
     /* connect powerdown request */
     qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
-- 
2.1.0