From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58398) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzn34-0005Gz-BL for qemu-devel@nongnu.org; Tue, 02 Jun 2015 10:20:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Yzn30-0007N2-Gj for qemu-devel@nongnu.org; Tue, 02 Jun 2015 10:20:10 -0400 Received: from mx1.redhat.com ([209.132.183.28]:39971) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Yzn30-0007KZ-CZ for qemu-devel@nongnu.org; Tue, 02 Jun 2015 10:20:06 -0400 Date: Tue, 2 Jun 2015 16:20:00 +0200 From: Igor Mammedov Message-ID: <20150602162000.04216a3e@nial.brq.redhat.com> In-Reply-To: <1432929154-11818-1-git-send-email-ehabkost@redhat.com> References: <1432929154-11818-1-git-send-email-ehabkost@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] target-i386: Fix signedness of MSR_IA32_APICBASE_BASE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduardo Habkost Cc: Peter Maydell , zhugh.fnst@cn.fujitsu.com, qemu-devel@nongnu.org, Paolo Bonzini , Andreas =?UTF-8?B?RsOkcmJlcg==?= , Richard Henderson On Fri, 29 May 2015 16:52:34 -0300 Eduardo Habkost wrote: > Existing definition triggers the following when using clang > -fsanitize=undefined: > > hw/intc/apic_common.c:314:55: runtime error: left shift of 1048575 by 12 > places cannot be represented in type 'int' > > Fix it so we won't try to shift a 1 to the sign bit of a signed integer. > > Suggested-by: Peter Maydell > Signed-off-by: Eduardo Habkost Reviewed-by: Igor Mammedov > --- > target-i386/cpu.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index 4ee12ca..26182bd 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -305,7 +305,7 @@ > #define MSR_IA32_APICBASE 0x1b > #define MSR_IA32_APICBASE_BSP (1<<8) > #define MSR_IA32_APICBASE_ENABLE (1<<11) > -#define MSR_IA32_APICBASE_BASE (0xfffff<<12) > +#define MSR_IA32_APICBASE_BASE (0xfffffU<<12) > #define MSR_IA32_FEATURE_CONTROL 0x0000003a > #define MSR_TSC_ADJUST 0x0000003b > #define MSR_IA32_TSCDEADLINE 0x6e0