From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34447) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z09kp-0003OA-F9 for qemu-devel@nongnu.org; Wed, 03 Jun 2015 10:34:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z09kn-00021w-9J for qemu-devel@nongnu.org; Wed, 03 Jun 2015 10:34:50 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:101::1]:38428) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z09kn-00021T-2n for qemu-devel@nongnu.org; Wed, 03 Jun 2015 10:34:49 -0400 Date: Wed, 3 Jun 2015 16:34:46 +0200 From: Aurelien Jarno Message-ID: <20150603143446.GA24650@aurel32.net> References: <1433194188-24514-1-git-send-email-aurelien@aurel32.net> <1433194188-24514-2-git-send-email-aurelien@aurel32.net> <556E35CB.3070703@codeaurora.org> <20150603070943.GQ26298@aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20150603070943.GQ26298@aurel32.net> Subject: Re: [Qemu-devel] [PULL 1/8] target-sh4: use bit number for SR constants List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Christopher Covington , qemu-devel@nongnu.org On 2015-06-03 09:09, Aurelien Jarno wrote: > On 2015-06-02 19:01, Christopher Covington wrote: > > Hi Aurelien, > >=20 > > On 06/01/2015 05:29 PM, Aurelien Jarno wrote: > > > Use the bit number for SR constants instead of using a bit mask. This > > > make possible to also use the constants for shifts. > > >=20 > > > Reviewed-by: Richard Henderson > > > Signed-off-by: Aurelien Jarno > > > --- > > > target-sh4/cpu.c | 3 +- > > > target-sh4/cpu.h | 30 ++++++++++---------- > > > target-sh4/gdbstub.c | 4 +-- > > > target-sh4/helper.c | 27 +++++++++--------- > > > target-sh4/op_helper.c | 26 ++++++++--------- > > > target-sh4/translate.c | 75 ++++++++++++++++++++++++++--------------= ---------- > > > 6 files changed, 85 insertions(+), 80 deletions(-) > > >=20 > > > diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c > > > index d187a2b..cccb14f 100644 > > > --- a/target-sh4/cpu.c > > > +++ b/target-sh4/cpu.c > > > @@ -61,7 +61,8 @@ static void superh_cpu_reset(CPUState *s) > > > env->fpscr =3D FPSCR_PR; /* value for userspace according to the= kernel */ > > > set_float_rounding_mode(float_round_nearest_even, &env->fp_statu= s); /* ?! */ > > > #else > > > - env->sr =3D SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I= 0; > > > + env->sr =3D (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | > > > + (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u <<= SR_I0); > >=20 > > I like using the BIT() macro for this kind of thing. >=20 > Thanks for the hint, I'll come with an additional patch to fix that in > the code. Unfortunately it doesn't seem as easy as it appears. The BIT() macro uses long types, so you can't invert it to create a mask without casting it first, otherwise GCC complains. For example: | target-sh4/translate.c: In function =E2=80=98_decode_opc=E2=80=99: | target-sh4/translate.c:408:42: error: large integer implicitly truncated = to unsigned type [-Werror=3Doverflow] | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~BIT(SR_S)); --=20 Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net