From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49055) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0Uc5-0005Ot-RM for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:51:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0Uc4-00083i-Pe for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:51:13 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44014) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0Uc4-00083U-Kf for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:51:12 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (Postfix) with ESMTPS id 3BADB2C76E6 for ; Thu, 4 Jun 2015 12:51:12 +0000 (UTC) Date: Thu, 4 Jun 2015 14:51:09 +0200 From: "Michael S. Tsirkin" Message-ID: <20150604145059-mutt-send-email-mst@redhat.com> References: <1433351328-23326-1-git-send-email-pbonzini@redhat.com> <1433351328-23326-19-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1433351328-23326-19-git-send-email-pbonzini@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 18/23] q35: fix ESMRAMC default List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: lersek@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com On Wed, Jun 03, 2015 at 07:08:43PM +0200, Paolo Bonzini wrote: > From: Gerd Hoffmann > > The cache bits in ESMRAMC are hardcoded to 1 (=disabled) according to > the q35 mch specs. Add and use a define with this default. > > While being at it also update the SMRAM default to use the name (no code > change, just makes things a bit more readable). > > Signed-off-by: Gerd Hoffmann > Signed-off-by: Paolo Bonzini Reviewed-by: Michael S. Tsirkin > --- > hw/pci-host/q35.c | 1 + > include/hw/pci-host/q35.h | 7 ++++++- > 2 files changed, 7 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 92804fe..93bec84 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -354,6 +354,7 @@ static void mch_reset(DeviceState *qdev) > MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); > > d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; > + d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; > > mch_update(mch); > } > diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h > index 0fff6a2..d3c7bbb 100644 > --- a/include/hw/pci-host/q35.h > +++ b/include/hw/pci-host/q35.h > @@ -128,7 +128,6 @@ typedef struct Q35PCIHost { > > #define MCH_HOST_BRIDGE_SMRAM 0x9d > #define MCH_HOST_BRIDGE_SMRAM_SIZE 2 > -#define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2) > #define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6)) > #define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5)) > #define MCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4)) > @@ -139,6 +138,8 @@ typedef struct Q35PCIHost { > #define MCH_HOST_BRIDGE_SMRAM_C_END 0xc0000 > #define MCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000 > #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 > +#define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ > + MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG > > #define MCH_HOST_BRIDGE_ESMRAMC 0x9e > #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) > @@ -151,6 +152,10 @@ typedef struct Q35PCIHost { > #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1)) > #define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1)) > #define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1) > +#define MCH_HOST_BRIDGE_ESMRAMC_DEFAULT \ > + (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ > + MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ > + MCH_HOST_BRIDGE_ESMRAMC_SM_L2) > > /* D1:F0 PCIE* port*/ > #define MCH_PCIE_DEV 1 > -- > 2.4.1 >