From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49189) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0UcS-000655-Vn for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:51:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0UcS-0000DU-6k for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:51:36 -0400 Received: from mx1.redhat.com ([209.132.183.28]:36431) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0UcS-0000DL-2n for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:51:36 -0400 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) by mx1.redhat.com (Postfix) with ESMTPS id ABE7E370226 for ; Thu, 4 Jun 2015 12:51:35 +0000 (UTC) Date: Thu, 4 Jun 2015 14:51:33 +0200 From: "Michael S. Tsirkin" Message-ID: <20150604145118-mutt-send-email-mst@redhat.com> References: <1433351328-23326-1-git-send-email-pbonzini@redhat.com> <1433351328-23326-20-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1433351328-23326-20-git-send-email-pbonzini@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 19/23] q35: add config space wmask for SMRAM and ESMRAMC List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: lersek@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com On Wed, Jun 03, 2015 at 07:08:44PM +0200, Paolo Bonzini wrote: > From: Gerd Hoffmann > > Not all bits in SMRAM and ESMRAMC can be changed by the guest. > Add wmask defines accordingly and set them in mch_reset(). > > Signed-off-by: Gerd Hoffmann > Signed-off-by: Paolo Bonzini Reviewed-by: Michael S. Tsirkin > --- > hw/pci-host/q35.c | 2 ++ > include/hw/pci-host/q35.h | 9 +++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 93bec84..ce101e2 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -355,6 +355,8 @@ static void mch_reset(DeviceState *qdev) > > d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; > d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; > + d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; > + d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; > > mch_update(mch); > } > diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h > index d3c7bbb..01b8492 100644 > --- a/include/hw/pci-host/q35.h > +++ b/include/hw/pci-host/q35.h > @@ -140,6 +140,11 @@ typedef struct Q35PCIHost { > #define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000 > #define MCH_HOST_BRIDGE_SMRAM_DEFAULT \ > MCH_HOST_BRIDGE_SMRAM_C_BASE_SEG > +#define MCH_HOST_BRIDGE_SMRAM_WMASK \ > + (MCH_HOST_BRIDGE_SMRAM_D_OPEN | \ > + MCH_HOST_BRIDGE_SMRAM_D_CLS | \ > + MCH_HOST_BRIDGE_SMRAM_D_LCK | \ > + MCH_HOST_BRIDGE_SMRAM_G_SMRAME) > > #define MCH_HOST_BRIDGE_ESMRAMC 0x9e > #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) > @@ -156,6 +161,10 @@ typedef struct Q35PCIHost { > (MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE | \ > MCH_HOST_BRIDGE_ESMRAMC_SM_L1 | \ > MCH_HOST_BRIDGE_ESMRAMC_SM_L2) > +#define MCH_HOST_BRIDGE_ESMRAMC_WMASK \ > + (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \ > + MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \ > + MCH_HOST_BRIDGE_ESMRAMC_T_EN) > > /* D1:F0 PCIE* port*/ > #define MCH_PCIE_DEV 1 > -- > 2.4.1 >