From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0Ucp-0006kH-Pa for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:52:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0Uco-0000Lv-2g for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:51:59 -0400 Received: from mx1.redhat.com ([209.132.183.28]:44232) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0Ucn-0000Lc-UP for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:51:58 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) by mx1.redhat.com (Postfix) with ESMTPS id 772A92CD833 for ; Thu, 4 Jun 2015 12:51:57 +0000 (UTC) Date: Thu, 4 Jun 2015 14:51:54 +0200 From: "Michael S. Tsirkin" Message-ID: <20150604145146-mutt-send-email-mst@redhat.com> References: <1433351328-23326-1-git-send-email-pbonzini@redhat.com> <1433351328-23326-21-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1433351328-23326-21-git-send-email-pbonzini@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 20/23] q35: implement SMRAM.D_LCK List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: lersek@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com On Wed, Jun 03, 2015 at 07:08:45PM +0200, Paolo Bonzini wrote: > From: Gerd Hoffmann > > Once the SMRAM.D_LCK bit has been set by the guest several bits in SMRAM > and ESMRAMC become readonly until the next machine reset. Implement > this by updating the wmask accordingly when the guest sets the lock bit. > As the lock it itself is locked down too we don't need to worry about > the guest clearing the lock bit. > > Signed-off-by: Gerd Hoffmann > Signed-off-by: Paolo Bonzini Reviewed-by: Michael S. Tsirkin > --- > hw/pci-host/q35.c | 8 +++++++- > include/hw/pci-host/q35.h | 3 +++ > 2 files changed, 10 insertions(+), 1 deletion(-) > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index ce101e2..2f37c29 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -268,6 +268,13 @@ static void mch_update_smram(MCHPCIState *mch) > PCIDevice *pd = PCI_DEVICE(mch); > bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); > > + /* implement SMRAM.D_LCK */ > + if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { > + pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; > + pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; > + pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; > + } > + > memory_region_transaction_begin(); > > if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { > @@ -297,7 +304,6 @@ static void mch_write_config(PCIDevice *d, > { > MCHPCIState *mch = MCH_PCI_DEVICE(d); > > - /* XXX: implement SMRAM.D_LOCK */ > pci_default_write_config(d, address, val, len); > > if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, > diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h > index 01b8492..113cbe8 100644 > --- a/include/hw/pci-host/q35.h > +++ b/include/hw/pci-host/q35.h > @@ -145,6 +145,8 @@ typedef struct Q35PCIHost { > MCH_HOST_BRIDGE_SMRAM_D_CLS | \ > MCH_HOST_BRIDGE_SMRAM_D_LCK | \ > MCH_HOST_BRIDGE_SMRAM_G_SMRAME) > +#define MCH_HOST_BRIDGE_SMRAM_WMASK_LCK \ > + MCH_HOST_BRIDGE_SMRAM_D_CLS > > #define MCH_HOST_BRIDGE_ESMRAMC 0x9e > #define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 7)) > @@ -165,6 +167,7 @@ typedef struct Q35PCIHost { > (MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME | \ > MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK | \ > MCH_HOST_BRIDGE_ESMRAMC_T_EN) > +#define MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK 0 > > /* D1:F0 PCIE* port*/ > #define MCH_PCIE_DEV 1 > -- > 2.4.1 >