From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49973) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0UeI-0001LU-SH for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:53:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0UeE-00013o-Ka for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:53:30 -0400 Received: from mx1.redhat.com ([209.132.183.28]:37528) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0UeE-00012b-Cd for qemu-devel@nongnu.org; Thu, 04 Jun 2015 08:53:26 -0400 Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) by mx1.redhat.com (Postfix) with ESMTPS id DF5643725A3 for ; Thu, 4 Jun 2015 12:53:25 +0000 (UTC) Date: Thu, 4 Jun 2015 14:53:23 +0200 From: "Michael S. Tsirkin" Message-ID: <20150604145317-mutt-send-email-mst@redhat.com> References: <1433351328-23326-1-git-send-email-pbonzini@redhat.com> <1433351328-23326-24-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1433351328-23326-24-git-send-email-pbonzini@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 23/23] ich9: implement SMI_LOCK List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: lersek@redhat.com, qemu-devel@nongnu.org, kraxel@redhat.com On Wed, Jun 03, 2015 at 07:08:48PM +0200, Paolo Bonzini wrote: > From: Gerd Hoffmann > > Add write mask for the smi enable register, so we can disable write > access to certain bits. Open all bits on reset. Disable write access > to GBL_SMI_EN when SMI_LOCK (in ich9 lpc pci config space) is set. > Write access to SMI_LOCK itself is disabled too. > > Signed-off-by: Gerd Hoffmann > Signed-off-by: Paolo Bonzini Reviewed-by: Michael S. Tsirkin > --- > hw/acpi/ich9.c | 4 +++- > hw/isa/lpc_ich9.c | 19 +++++++++++++++++++ > include/hw/acpi/ich9.h | 1 + > include/hw/i386/ich9.h | 6 ++++++ > 4 files changed, 29 insertions(+), 1 deletion(-) > > diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c > index 84e5bb8..ec0e008 100644 > --- a/hw/acpi/ich9.c > +++ b/hw/acpi/ich9.c > @@ -94,7 +94,8 @@ static void ich9_smi_writel(void *opaque, hwaddr addr, uint64_t val, > ICH9LPCPMRegs *pm = opaque; > switch (addr) { > case 0: > - pm->smi_en = val; > + pm->smi_en &= ~pm->smi_en_wmask; > + pm->smi_en |= (val & pm->smi_en_wmask); > break; > } > } > @@ -198,6 +199,7 @@ static void pm_reset(void *opaque) > * support SMM mode. */ > pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN; > } > + pm->smi_en_wmask = ~0; > > acpi_update_sci(&pm->acpi_regs, pm->irq); > } > diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c > index dba7585..0269cfe 100644 > --- a/hw/isa/lpc_ich9.c > +++ b/hw/isa/lpc_ich9.c > @@ -410,12 +410,28 @@ static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rbca_old) > } > } > > +/* config:GEN_PMCON* */ > +static void > +ich9_lpc_pmcon_update(ICH9LPCState *lpc) > +{ > + uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); > + uint16_t wmask; > + > + if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { > + wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); > + wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; > + pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); > + lpc->pm.smi_en_wmask &= ~1; > + } > +} > + > static int ich9_lpc_post_load(void *opaque, int version_id) > { > ICH9LPCState *lpc = opaque; > > ich9_lpc_pmbase_update(lpc); > ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */); > + ich9_lpc_pmcon_update(lpc); > return 0; > } > > @@ -438,6 +454,9 @@ static void ich9_lpc_config_write(PCIDevice *d, > if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { > pci_bus_fire_intx_routing_notifier(lpc->d.bus); > } > + if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { > + ich9_lpc_pmcon_update(lpc); > + } > } > > static void ich9_lpc_reset(DeviceState *qdev) > diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h > index c2d3dba..77cc65c 100644 > --- a/include/hw/acpi/ich9.h > +++ b/include/hw/acpi/ich9.h > @@ -39,6 +39,7 @@ typedef struct ICH9LPCPMRegs { > MemoryRegion io_smi; > > uint32_t smi_en; > + uint32_t smi_en_wmask; > uint32_t smi_sts; > > qemu_irq irq; /* SCI */ > diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h > index f4e522c..a2cc15c 100644 > --- a/include/hw/i386/ich9.h > +++ b/include/hw/i386/ich9.h > @@ -152,6 +152,12 @@ Object *ich9_lpc_find(void); > #define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0) > #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80 > > +#define ICH9_LPC_GEN_PMCON_1 0xa0 > +#define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4) > +#define ICH9_LPC_GEN_PMCON_2 0xa2 > +#define ICH9_LPC_GEN_PMCON_3 0xa4 > +#define ICH9_LPC_GEN_PMCON_LOCK 0xa6 > + > #define ICH9_LPC_RCBA 0xf0 > #define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14) > #define ICH9_LPC_RCBA_EN 0x1 > -- > 2.4.1