From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46258) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0fof-0005Bc-Se for qemu-devel@nongnu.org; Thu, 04 Jun 2015 20:48:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Z0foc-0007IK-JJ for qemu-devel@nongnu.org; Thu, 04 Jun 2015 20:48:57 -0400 Received: from mail-bl2on0082.outbound.protection.outlook.com ([65.55.169.82]:13536 helo=na01-bl2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Z0foc-0007IG-En for qemu-devel@nongnu.org; Thu, 04 Jun 2015 20:48:54 -0400 Received: from unknown-38-66.xilinx.com ([149.199.38.66] helo=xsj-pvapsmtp01) by xsj-pvapsmtpgw01 with esmtp (Exim 4.63) (envelope-from ) id 1Z0foZ-00038G-Sc for qemu-devel@nongnu.org; Thu, 04 Jun 2015 17:48:51 -0700 Received: from [127.0.0.1] (helo=localhost) by xsj-pvapsmtp01 with smtp (Exim 4.63) (envelope-from ) id 1Z0foZ-0001eq-NQ for qemu-devel@nongnu.org; Thu, 04 Jun 2015 17:48:51 -0700 Date: Fri, 5 Jun 2015 10:44:33 +1000 From: "Edgar E. Iglesias" Message-ID: <20150605004433.GT17878@toto> References: <7fda3e173be8b145bbddbf3a14aacc575a7bf47a.1433314301.git.alistair.francis@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <7fda3e173be8b145bbddbf3a14aacc575a7bf47a.1433314301.git.alistair.francis@xilinx.com> Subject: Re: [Qemu-devel] [PATCH RESEND v1 5/8] target-microblaze: Convert pvr-full to a CPU property List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alistair Francis Cc: peter.crosthwaite@xilinx.com, qemu-devel@nongnu.org On Thu, Jun 04, 2015 at 11:23:57AM +1000, Alistair Francis wrote: > Originally the pvr-full PVR bits were manually set for each machine. This > is a hassle and difficult to read, instead set them based on the CPU > properties. > > Signed-off-by: Alistair Francis > --- > target-microblaze/cpu-qom.h | 1 + > target-microblaze/cpu.c | 7 ++++--- > target-microblaze/helper.c | 4 ++-- > 3 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h > index b6c6374..799f5b8 100644 > --- a/target-microblaze/cpu-qom.h > +++ b/target-microblaze/cpu-qom.h > @@ -68,6 +68,7 @@ typedef struct MicroBlazeCPU { > bool dcache_writeback; > bool endi; > bool version_mask; > + bool pvr_full; > } cfg; > > CPUMBState env; > diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c > index 849c737..329d4d5 100644 > --- a/target-microblaze/cpu.c > +++ b/target-microblaze/cpu.c > @@ -91,8 +91,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > > qemu_init_vcpu(cs); > > - env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ > - | PVR0_USE_BARREL_MASK \ > + env->pvr.regs[0] = PVR0_USE_BARREL_MASK \ > | PVR0_USE_DIV_MASK \ > | PVR0_USE_HW_MUL_MASK \ > | PVR0_USE_EXC_MASK \ > @@ -116,7 +115,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) > (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0) | > (cpu->cfg.usemmu ? PVR0_USE_MMU_MASK : 0) | > (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | > - (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0); > + (cpu->cfg.endi ? ~PVR0_VERSION_MASK : 0) | > + (cpu->cfg.pvr_full ? PVR0_PVR_FULL_MASK : 0); > > env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) | > (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0); > @@ -178,6 +178,7 @@ static Property mb_properties[] = { > false), > DEFINE_PROP_BOOL("endi", MicroBlazeCPU, cfg.endi, false), > DEFINE_PROP_BOOL("version-mask", MicroBlazeCPU, cfg.version_mask, false), > + DEFINE_PROP_BOOL("pvr-full", MicroBlazeCPU, cfg.pvr_full, true), This is another one with wierdo dts mapping. You can look our tree hw/microblaze/microblaze_generic_fdt.c to figure it out. > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c > index b310c2b..55b92e2 100644 > --- a/target-microblaze/helper.c > +++ b/target-microblaze/helper.c > @@ -58,8 +58,8 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw, > mmu_available = 0; > if (cpu->cfg.usemmu) { > mmu_available = 1; > - if ((env->pvr.regs[0] & PVR0_PVR_FULL_MASK) > - && (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { > + if (cpu->cfg.pvr_full && > + (env->pvr.regs[11] & PVR11_USE_MMU) != PVR11_USE_MMU) { > mmu_available = 0; > } > } > -- > 1.7.1 >