Re: [Qemu-devel] [PATCH 01/13] target-mips: fix {D, W}RGPR in microMIPS

[Aurelien Jarno <aurelien@aurel32.net>]

On 2015-06-12 15:02, Yongbok Kim wrote:
> rt, rs were swapped
> 
> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
> ---
>  target-mips/translate.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index f6ae0d3..d4a530d 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -12749,12 +12749,12 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
>          case RDPGPR:
>              check_cp0_enabled(ctx);
>              check_insn(ctx, ISA_MIPS32R2);
> -            gen_load_srsgpr(rt, rs);
> +            gen_load_srsgpr(rs, rt);
>              break;
>          case WRPGPR:
>              check_cp0_enabled(ctx);
>              check_insn(ctx, ISA_MIPS32R2);
> -            gen_store_srsgpr(rt, rs);
> +            gen_store_srsgpr(rs, rt);
>              break;
>          default:
>              goto pool32axf_invalid;

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

Note however that your subject should be {RD,WR}PGPR to correctly match
both instructions.


-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net